This paper presents a sub-1V delta-sigma modulator (DSM) with power and bandwidth (BW) scalability for IoT applications. It is built around a fully dynamic and low-voltage floating inverter amplifier (LVFIA). To extend the power and BW scalability of the LVFIA, its relatively supply-independent bias current is auto-controlled by DSM’s sampling frequency$f_{s}$. Dynamic techniques such as auto-zeroing and chopping are applied to achieve low noise. Fabricated in a 130nm CMOS, the proposed sub-1V DSM shows a near-consistent SNDR (~90dB) and linearly scalable power and BW (2.5nW/Hz) over a$\times 30$scaling range of$f_{s}$. It achieves Walden FoM and Schreier FoM of 51.3fJ/conv-step and 175.7dB, respectively.

This paper presents a power-efficient and quickly-settled chopper-stabilized capacitively coupled instrumentation amplifier (CCIA) for neural recording applications. To achieve a relatively-low high-pass corner frequency while achieving fast-settling, a duty-cycled resistor (DCR) based very-large time constant (VLT) integrator is proposed. By stacking inverters and splitting the input capacitor network, the input stage of the CCIA achieves four-time current reuse, significantly improving the power-efficiency. A prototype in 180-nm CMOS technology has 2.2µV input-referred noise (IRN) with 5kHz bandwidth (BW) while consuming only 2.92µA current from a 1.2V supply, achieving a noise efficiency factor (NEF) of 2.1 and a power efficiency factor (PEF) of 5.2. Simulations show that it can settle within 10ms after powering on with a maximum electrode DC offset of 50 mV.

Sparse general matrix multiplication (SpGEMM) is a fundamental building block in numerous scientific applications. One critical task of SpGEMM is to compute or predict the structure of the output matrix (i.e., the number of nonzero elements per output row) for efficient memory allocation and load balance, which impact the overall performance of SpGEMM. Existing work either precisely calculates the output structure or adopts upper-bound or sampling-based methods to predict the output structure. However, these methods either take much execution time or are not accurate enough. In this paper, we propose a novel sampling-based method with better accuracy and low costs compared to the existing sampling-based method. The proposed method first predicts the compression ratio of SpGEMM by leveraging the number of intermediate products (denoted as FLOP) and the number of nonzero elements (denoted as NNZ) of the same sampled result matrix. And then, the predicted output structure is obtained by dividing the FLOP per output row by the predicted compression ratio. We also propose a reference design of the existing sampling-based method with optimized computing overheads to demonstrate the better accuracy of the proposed method. We construct 623 test cases with various matrix dimensions and sparse structures to evaluate the prediction accuracy. Experimental results show that the absolute relative errors of the proposed method and the reference design are 1.30% and 7.93%, respectively, on average, and 25% and 158%, respectively, in the worst case.

This paper presents an energy metering and measurement system-on-a-chip (SoC) with a novel low-power digital signal processor (DSP) architecture. The Cotex-M0-based SoC can measure electricity signals and meter active and reactive energy. It can also monitor the grid by directly accessing and analyzing the waveforms. The measurement and metering algorithms are implemented in a novel DSP architecture with a dedicated reduced instruction set. The filter coefficients and its operating frequency in the default program of DSP can be reprogrammed independently. It can be applied in different applications where demands for metering bandwidth and response time are different. The DSP program can also be reprogrammed by the software if the default program is not desired. The SoC is implemented in a 0.11-μm CMOS process. It achieves active and reactive energy metering accuracy of 0.1% with a dynamic range of 5000:1. The analog power supply is 3.3 V and the digital power supply is 1.8 V. The total power consumption of the SoC is ca 17.63 mW with the DSP consuming ca 1.0 mW. Compared with other commercial metering and measurement SoCs, the presented SoC achieves higher metering accuracy and lower power consumption. It is currently in production.

It is difficult to analyze the harmonic distortion of a self-oscillating power amplifier (SOPA), because the SOPA is a hard nonlinear system without an external clock. The single or multiple sinusoidal inputs describing function (DF) method is commonly used to linearize a nonlinear element, but this method considers only the components at the same frequencies as the input signals (i.e., fundamental components) at the nonlinear element’s output. In this paper, besides the fundamental components, the third harmonic components are also calculated at the output of a comparator with three sinusoidal inputs, to create a linearized model of the comparator, and thus of the SOPA. The third harmonic distortion of the SOPA is calculated. The models of the zeroth and the first order SOPA are verified by behavioral simulation using MATLAB.

In high order single loop continuous-time (CT) sigma delta modulators, excess loop delay may cause instability. In this paper, previous techniques in compensation of internal quantizer and feedback DAC delays are studied especially for the feedforward structure. Two alternative low power feedforward continuous-time sigma delta modulators with excess loop delay compensation are proposed. Simulation based CT synthesis from discrete time topologies is adopted to obtain the loop filter coefficients. Design examples are given to illustrate the proposed structure and the synthesis methodology.

Practical considerations restrict the usefulness of all but the simplest comb filters as the first-stage decimators in oversampling delta-sigma A/D converters due to the large oversampling ratios. A design technique is thereupon presented for two-stage decimators in oversampling delta-sigma A/D converters. This design technique takes into account the noise shaping in the delta-sigma modulator and the requirements of the whole A/D converter in order to optimize the decimator. The optimum decimators are also derived in order to achieve the maximum resolution performance.>

This paper presents the design of a fully differential second-order delta-sigma modulator using a single 3.3-V power supply voltage. At the system level, we tailor the modulator structure considering the similarity and difference of switched-capacitor and switched-current realizations. At the circuit level, we propose a new switched-current memory cell and integrator with improved common mode feedback, without which low power-supply-voltage operation would not be possible. Other building blocks such as 1-bit A/D and D/A converters are presented as well. The whole modulator has been implemented in AMS' 0.8-/spl mu/m double-metal digital CMOS process. It occupies an active area of 0.53/spl times/0.48 mm/sup 2/ and consumes a current of 0.6 mA.>

The bit-serial processing technique arises to be a competitor of the traditional bit-parallel processing technique to implement DSP ASICs, because the bit-serial implementation of DSP ASICs usually results in small communication cost and compact processing elements. However, shift registers are usually used to realize delays required by the DSP algorithms. Long shift registers consume a lot of power for they are clocked at very high frequency. More troublesome is that the power associated with driving a lot of clocked transistors has to be supplied by the clock lines (not power supply lines), which may cause clock distribution problem. In this paper, we propose a power-saving technique without speed penalty by getting rid of unnecessary data shifting and long shift registers. All the delay elements in the traditional long shift registers are realized by DRAM-alike memory cells and data is not shifted but accessed by using shared cyclical address decoders. The measurement of a test chip indicates a power saving by 4 times when we need to use 15 16-bit shift registers. More power saving is expected when we need more shift registers for large DSP ASICs.>

The non-recursive algorithm of comb filters suitable for bit-serial implementation is described in this paper. It performs decimation on the oversampling delta-sigma modulator output in several stages by utilizing the commutative rule. Each stage performs very simple FIR filtering and decimates the output by a factor of 2. A novel bit-serial design based on this algorithm is then presented. It features regularity and area and power-consumption efficiency. It also provides the possibility of higher frequency operation than existing designs. As an example, a comb filter of the response sinc/sup 3/(f) with a decimation ratio 32 has been designed in AMS' 1 /spl mu/m double-metal CMOS process. It contains only 4500 transistors even by using standard static gates and occupies about 1.1 mm/sup 2/ active chip area.>