The computing community has produced many high level languages and tools for programming high level systems (e.g. Java for user interfaces) and it has produced many low level languages and tools for programming low level systems (C for operating systems, Verilog for hardware design) yet there are not many examples of high level systems that have been produced to help develop low level systems. Sometimes this is due to a suspicion that the layers of abstraction that high level systems use incur unacceptable performance overheads. However, this talk attempts to challenge that view, giving examples of high level systems that improve the designer productivity for developing low level systems which also improve the quality of verification for low level systems. The talk will draw examples from the presenter’s own experience, as well as the work of others. Specific examples will include Lava and Bluespec for the design of hardware, the Silver Oak project for the co-design of a high assurance silicon root of trust, a Haskell-based DSL for programming machine learning chips, and recent work on the specification and verification of parts of a new silicon chip produced at Groq which makes use of the same Haskell DSL.

FPGAs and other 2D and 3D spatial computing fabrics share several common characteristics e.g. a deterministic computing model with distributed memories, but also differ along important dimensions e.g. granularity and communication infrastructure. This talk will position Groq's Tensor Streaming Processing (TSP) chip relative to other spatial computing fabrics and highlight common aspects of programming models for such spatial computing engines as well as highlighting some of the unique characteristics of the TSP architecture and its programming model One common characteristic this talk will focus on is \em determinism and specifically the use of static scheduling to know at compile time exactly how many cycles a program will take to execute regardless of the specific values of the input data to the TSP chip. Groq's TSP architecture is based on a parallel collection of coarse grain processing units including matrix multiplication or convolution (MXM), vector operations (VXM), arbitrary vector transformations (SXM) and various numerical operations. Data originates from a memory reads (MEM) and is then chained through a tensor pipeline through one or more computing blocks and terminated by a memory write (MEM). The chip can operate on in-flight tensors as they are produced and consumed, aggressively exploiting data-flow locality. A variety of deterministic computing models will be surveyed as we seek abstractions that support rapid multiplexing between multiple workloads which can be co-resident on TSP chips, with scheduling and coordination facilitated by determinism.

The 17th ACM SIGPLAN International Conference on Functional Programming (ICFP) took place on September 10–12, 2012 in Copenhagen, Denmark. After the conference, the programme committee selected several outstanding papers and invited their authors to submit to this special issue of Journal of Functional Programming . Robby Findler and Satnam Singh acted as editors for these submissions. This issue includes the accepted papers, each of which provides substantial new material beyond the original conference version.

Fault dependency (D)-matrix is a systematic diagnostic model [7] to capture the hierarchical system-level fault diagnostic information consisting of dependencies between observable symptoms and failure modes associated with a system. Constructing a D-matrix from first principles and updating it using the domain knowledge is a labor intensive and time consuming task. Further, in-time augmentation of D-matrix through the discovery of new symptoms and failure modes observed for the first time is a challenging task. Here, we describe an ontology-based text mining method for automatically constructing and updating a D-matrix by mining hundreds of thousands of repair verbatim (typically written in unstructured text) collected during the diagnosis episodes. In our approach, we first construct the fault diagnosis ontology consisting of concepts and relationships commonly observed in the fault diagnosis domain. Next, we employ the text mining algorithms that make use of this ontology to identify the necessary artifacts, such as parts, symptoms, failure modes, and their dependencies from the unstructured repair verbatim text. The proposed method is implemented as a prototype tool and validated by using real-life data collected from the automobile domain.

The field of context and intelligence, as a topic of pervasive computing, has been gaining considerable momentum. Typically, context-aware intelligence is applied to understand the situation of the users and their behavior with the objective of providing adaptive services that are closely associated with that context. In this work, we have taken an orthogonal approach wherein we attempt to aggregate knowledge and cognition, of the user, on a given topic to build models out of them. The model thus created is analyzed to derive inferences about the user, where the analysis is performed on a graph model comprising topics based information obtained by mining domain specific personal data sources and from certain facts on which the user has expressed fair level of belief. We have explored the possibility of deriving beneficial information by provisioning an appropriate representation of knowledge as belief-graph with specific orientation in healthcare and call this model as Med-Tree. Subject to privacy conditions, we open up the belief-graph model to establish objective based social connections that gets contextually bound. As a next step, such contextually bound ad-hoc networks are subjected to advanced querying process resulting in useful information extraction and inferences. Leveraging on user's knowledge or the belief-graph, the proposed Med-Tree could help derive benefits towards better personal healthcare and disease management.

In this paper, we formulate a coupled factorial hidden Markov model-based (CFHMM) framework to diagnose dependent faults occurring over time (dynamic case). In our previous research, the problem of diagnosing multiple faults over time (dynamic multiple fault diagnosis (DMFD)) is solved based on a sequence of test outcomes by assuming that the faults and their time evolution are independent. This problem is NP-hard, and, consequently, we developed a polynomial approximation algorithm using Lagrangian relaxation within a FHMM framework. Here, we extend this formulation to a mixed memory Markov coupling model, termed dynamic coupled fault diagnosis (DCFD) problem, to determine the most likely sequence of (dependent) fault states, the one that best explains the observed test outcomes over time. An iterative Gauss-Seidel coordinate ascent optimization method is proposed for solving the DCFD problem. A soft Viterbi algorithm is also implemented within the framework for decoding-dependent fault states over time. We demonstrate the algorithm on simulated systems with coupled faults and the results show that this approach improves the correct isolation rate (CI) as compared to the formulation where independent fault states (DMFD) are assumed. As a by-product, we show empirically that, while diagnosing for independent faults, the DMFD algorithm based on block coordinate ascent method, although it does not provide a measure of suboptimality, provides better primal cost and higher CI than the Lagrangian relaxation method for independent fault case. Two real-world examples (a hybrid electric vehicle, and a mobile autonomous robot) with coupled faults are also used to evaluate the proposed framework.

The set-covering problem is widely used to model many real-world applications. In this paper, we formulate a generalization of set-covering, termed dynamic set-covering (DSC), which involves a series of coupled set-covering problems over time. We motivate the DSC problem from the viewpoint of a dynamic multiple fault diagnosis problem, wherein faults, possibly intermittent, evolve over time; the fault-test dependencies are deterministic (components associated with passed tests cannot be suspected to be faulty and at least one of the components associated with failed tests is faulty), and the test outcomes may be observed with delay. The objective of the DSC problem is to infer the most probable time sequence of a parsimonious set of failure sources that explains the observed test outcomes over time. The DSC problem is NP-hard and intractable due to the fault-test dependency matrix that couples the failed tests and faults via the constraint matrix, and the temporal dependence of failure sources over time. By relaxing the coupling constraints using Lagrange multipliers, the DSC problem can be decoupled into independent subproblems, one for each fault. Each subproblem is solved using the Viterbi decoding algorithm, and a primal feasible solution is constructed by modifying the Viterbi solutions via a heuristic. The Lagrange multipliers are updated using a subgradient method. The proposed Viterbi-Lagrangian relaxation algorithm provides a measure of suboptimality via an approximate duality gap. As a major practical extension of the above problem, we also consider the problem of diagnosing faults with delayed test outcomes, termed delay DSC. A detailed experimental evaluation of the algorithms is provided using real-world problems that exhibit masking faults.

This paper describes the compiler design for VENICE, a new soft vector processor (SVP). The compiler is a new back-end target for Microsoft Accelerator, a high-level data parallel library for C++ and C#. This allows us to automatically compile high-level programs into VENICE assembly code, thus avoiding the process of writing assembly code used by previous SVPs. Experimental results show the compiler can generate scalable parallel code with execution times that are comparable to hand-written VENICE assembly code. On data-parallel applications, VENICE at 100MHz on an Altera DE3 platform runs at speeds comparable to one core of a 3.5GHz Intel Xeon W3690 processor, beating it in performance on four of six benchmarks by up to 3.2x.

Intermittent failures can be problematic in electronic control units (ECUs) such as engine/transmission control modules. When an ECU exhibits an internal performance fault, the ECU may malfunction, while the fault condition is active, and later, it may once again give correct results when conditions change. Due to highly unpredictable nature of intermittent faults, it can be extremely difficult to diagnose them. Therefore, there is a need to enhance the fault diagnosis of intermittent faults in ECUs. In this paper, we propose an off-board, data-driven approach that can assist diagnostic engineers to investigate intermittent faults using fleet-wide field failure data. The field failure data may include a large number of intermittent faults and concomitant operating parameters (e.g., vehicle speed, engine speed, control module voltage, powertrain relay voltage, etc.) recorded at the time when the faults occurred. We describe a decision forest method to identify a reduced set of informative operating parameters, i.e., features that separate or characterize the operating conditions of the intermittent fault from baseline, i.e., classes in feature selection space. A web-based application has been developed to assist the diagnostic engineers. We demonstrate the capabilities of our method using three case studies for an automobile test fleet.

Reconfigurable computing in the cloud helps to solve many practical problems relating to scaling out data-centers where computation is limited by energy consumption or latency. However, for reconfigurable computing in the cloud to become practical several research challenges have to be addressed. This paper identifies some of the perquisites for reconfigurable computing systems in the cloud and picks out several scenarios made possible with immense cloud-based computing capability.

In this paper we present the design and implementation of TMbox: An MPSoC built to explore trade-offs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

Are user specified layout constraints of significant value anymore? Certainly in the past the use of the RLOC layout constraint for Xilinx FPGAs was essential for achieving the best possible performance for many kinds of highly structured designs. However, have CAD tools evolved to the point where they can always compute layouts as good as (if not better than) humans? Or has the introduction of on-chip hard cores, which create an irregular 2D surface for layouts, made layout specification impractical? Or has the varying pitch and types of combinational logic blocks (CLBs) made it intractable to produce layout descriptions that are portable across architectures? We show that the use of layout constraints still delivers a large performance gain for Xilinx's recent Virtex-6 family of FPGAs. The performance gain is sometime large enough to accommodate a reduction of two speed grades.

Abramsky's Geometry of Interaction interpretation (GoI) is a logical-directed way to reconcile the process and functional views of computation, and can lead to a dataflow-style semantics of programming languages that is both operational (i.e. effective) and denotational (i.e. inductive on the language syntax). The key idea of Ghica's Geometry of Synthesis (GoS) approach is that for certain programming languages (namely Reynolds's affine Syntactic Control of Interference - SCI) the GoI processes-like interpretation of the language can be given a finitary representation, for both internal state and tokens. A physical realisation of this representation becomes a semantics-directed compiler for SCI into hardware. In this paper we examine the issue of compiling affine recursive programs into hardware using the GoS method. We give syntax and compilation techniques for unfolding recursive computation in space or in time and we illustrate it with simple benchmark-style examples. We examine the performance of the benchmarks against conventional CPU-based execution models.

The Kiwi system achieves co-design by allowing nominated regions of C# programs to be targeted at FPGAs while the remainder executes on unmodified .NET and Mono virtual machines. Using C# attributes, certain methods are identified for separate compilation and collections of methods are mapped to multiple FPGAs or to workstations connected to a common Ethernet switch. Individual methods become RPC-callable entities for the top-level C# thread running on one workstation, while server threads may run continually on other workstations or FPGAs. We illustrate the concept using minimal modifications to an Adobe Photoshop plug-in where the processing for each colour channel is farmed over the Ethernet to one or three remote entities which may each be either an FPGA or a workstation.

This paper describes the techniques used to describe and synthesize FPGA circuits expressed in a data-parallel domain specific language (DSL) called Accelerator. We identify the subset of data-parallel descriptions that are supported by our system and explain how we track memory access patterns which allow us to generate efficient FPGA circuits.

Recent progress in program analysis has produced tools that are able to compute upper bounds on the use of dynamic memory. This opens up a space for the use of dynamic memory abstraction in high-level synthesis. In this paper, we explain how to design hardware using C programs with malloc() and free(). A compilation process is outlined for transforming C programs with heap operations into a hardware description language. As demonstrated by our experiments, this approach is feasible. Further, automatic parallelization of the generated circuits improves by a factor up to 1.9 in terms of clock frequency and a factor up to 2.7 in terms of clock cycles over the previous work.

This paper presents an investigation into the possibility of using a regular concurrent programming language for modeling and implementing digital circuits. Some of the reasons for using an existing language include the ability to use existing compilers and analysis tools for circuit design and verification. Another important reason is the ever increasing need to model complete systems that comprise interacting software and hardware in a single framework which facilitates easier migration of sub-components between hardware and software implementations compared to multi-model approaches. To this end we present the design of the Kiwi system which models digital circuits with concurrent programs using a standard library in C# for multi-threaded programming. Kiwi models can be executed using a regular C# compiler. Also, the compiled bytecode can be automatically converted into circuits using our Kiwi hardware synthesis system.

Abstract We present a case study showing how an existing concurrent programming language can be used to produce either efficient control‐oriented circuits or embedded software from the same description. This description is also amenable to fully automatic formal verification and can be used to produce pairs of reconfigurable components which can be dynamically scheduled into either hardware or software resources. By using an existing concurrent language we increase the productivity because we can make use of readily available tools for debugging, analysis and verification. We believe that a language and a system that generates good software and hardware is a promising starting point for helping mainstream software developers target future manycore systems which will comprise a mixture of software and hardware components as well as provide a valuable technique for producing interchangeable reconfigurable components for run‐time reconfigurable FPGAs. Copyright © 2007 S. Singh. [Correction made here after initial online publication]

Dynamically allocated and manipulated data structures cannot be translated into hardware unless there is an upper bound on the amount of memory the program uses during all executions. This bound can depend on the generic parameters to the program, i.e., program inputs that are instantiated at synthesis time. We propose a constraint based method for the discovery of memory usage bounds, which leads to the first-known C-to-gates hardware synthesis supporting programs with non-trivial use of dynamically allocated memory, e.g., linked lists maintained with malloc and free. We illustrate the practicality of our tool on a range of examples.

Parallel Haskell programming has entered the mainstream with support now included in GHC for multiple parallel programming models, along with multicore execution support in the runtime. However, tuning programs for parallelism is still something of a black art. Without much in the way of feedback provided by the runtime system, it is a matter of trial and error combined with experience to achieve good parallel speedups.

Purely functional programs should run well on parallel hardware because of the absence of side effects, but it has proved hard to realise this potential in practice. Plenty of papers describe promising ideas, but vastly fewer describe real implementations with good wall-clock performance. We describe just such an implementation, and quantitatively explore some of the complex design tradeoffs that make such implementations hard to build. Our measurements are necessarily detailed and specific, but they are reproducible, and we believe that they offer some general insights.

Imperfect test outcomes, due to factors such as unreliable sensors, electromagnetic interference, and environmental conditions, manifest themselves as missed detections and false alarms. This paper develops near-optimal algorithms for dynamic multiple fault diagnosis (DMFD) problems in the presence of imperfect test outcomes. The DMFD problem is to determine the most likely evolution of component states, the one that best explains the observed test outcomes. Here, we discuss four formulations of the DMFD problem. These include the deterministic situation corresponding to perfectly observed coupled Markov decision processes to several partially observed factorial hidden Markov models ranging from the case where the imperfect test outcomes are functions of tests only to the case where the test outcomes are functions of faults and tests, as well as the case where the false alarms are associated with the nominal (fault free) case only. All these formulations are intractable NP-hard combinatorial optimization problems. Our solution scheme can be viewed as a two-level coordinated solution framework for the DMFD problem. At the top (coordination) level, we update the Lagrange multipliers (coordination variables, dual variables) using the subgradient method. At the bottom level, we use a dynamic programming technique (specifically, the Viterbi decoding or Max-sum algorithm) to solve each of the subproblems, one for each component state sequence. The key advantage of our approach is that it provides an approximate duality gap, which is a measure of the suboptimality of the DMFD solution. Computational results on real-world problems are presented. A detailed performance analysis of the proposed algorithm is also discussed.

The problem of detecting an anomaly (or abnormal event) is such that the distribution of observations is different before and after an unknown onset time, and the objective is to detect the change by statistically matching the observed pattern with that predicted by a model. In the context of asymmetric threats, the detection of an abnormal situation refers to the discovery of suspicious activities of a hostile nation or group out of noisy, scattered, and partial intelligence data. The problem becomes complex in a low signal-to-noise ratio environment, such as asymmetric threats, because the ldquosignalrdquo observations are far fewer than ldquonoiserdquo observations. Furthermore, the signal observations are ldquohiddenrdquo in the noise. In this paper, we illustrate the capabilities of hidden Markov models (HMMs), combined with feature-aided tracking, for the detection of asymmetric threats. A transaction-based probabilistic model is proposed to combine HMMs and feature-aided tracking. A procedure analogous to Page's test is used for the quickest detection of abnormal events. The simulation results show that our method is able to detect the modeled pattern of an asymmetric threat with a high performance as compared to a maximum likelihood-based data mining technique. Performance analysis shows that the detection of HMMs improves with increase in the complexity of HMMs (i.e., the number of states in an HMM).

We describe the Kiwi parallel programming library and its associated synthesis system which is used to transform C# parallel programs into circuits for realization on FPGAs. The Kiwi system is targeted at making reconfigurable computing technology accessible to software engineers that are willing to express their computations as parallel programs. Although there has been much work on compiling sequential C-like programs to hardware by automatically `discovering¿ parallelism, we work by exploiting the parallel architecture communicated by the designer through the choice of parallel and concurrent programming language constructs. Specifically, we describe a system that takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to FPGAs. We can then choose to apply analysis and verification techniques to either the highlevel representation in C# or other .NET languages or to the generated RTL netlists. A distinctive aspect of our approach is the exploitation of existing language constructs for concurrent programming and synchronization which contrasts with other schemes which introduce specialized concurrency control constructs to extend a sequential language.

The Kiwi system is targeted at making reconfigurable computing technology accessible to software engineers that are willing to express their computations as parallel programs. Our kiwic compiler takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to FPGAs. In this brief paper, we describe attributes used to mark up I/O nets, embed assertions, and for other purposes.

The advent of multicore processors requires mainstream concurrent programming languages with high level concurrency constructs and effective debugging techniques. Unfortunately, many concurrent programming languages are non-deterministic and allow data races.

In this paper we present an automated way of using spare CPU resources within a shared memory multi-processor or multi-core machine. Our approach is (i) to profile the execution of a program, (ii) from this to identify pieces of work which are promising sources of parallelism, (iii) recompile the program with this work being performed speculatively via a work-stealing system and then (iv) to detect at run-time any attempt to perform operations that would reveal the presence of speculation.

In this paper, a hidden Markov model (HMM)-based dynamic sensor scheduling problem is formulated, and solved using rollout concepts to overcome the computational intractability of the dynamic programming (DP) recursion. The problem considered here involves dynamically sequencing a set of sensors to minimize the sum of sensor cost and the HMM state estimation error cost. The surveillance task is modeled as a single HMM with multiple emission matrices corresponding to each of the sensors. The rollout information gain (RIG) algorithm proposed herein employs the information gain (IG) heuristic as the base algorithm. The RIG algorithm is illustrated on an intelligence, surveillance, and reconnaissance (ISR) scenario of a village for the presence of weapons and terrorists/refugees. Extension of the RIG strategy to monitor multiple HMMs involves combining the information gain heuristic with the auction algorithm that computes the κ-best assignments at each decision epoch of rollout.

This paper considers the problem of temporally fusing classifier outputs to improve the overall diagnostic classification accuracy in safety-critical systems. Here, we discuss dynamic fusion of classifiers which is a special case of the dynamic multiple fault diagnosis (DMFD) problem [1]–[3]. The DMFD problem is formulated as a maximum a posteriori (MAP) configuration problem in tri-partite graphical models, which is NP-hard. A primal-dual optimization framework is applied to solve the MAP problem. Our process for dynamic fusion consists of four key steps: (1) data preprocessing such as noise suppression, data reduction and feature selection using data-driven techniques, (2) error correcting codes to transform the multiclass data into binary classification, (3) fault detection using pattern recognition techniques (support vector machines in this paper), and (4) dynamic fusion of classifiers output labels over time using the DMFD algorithm. An automobile engine data set, simulated under various fault conditions [4], was used to illustrate the fusion process. The results demonstrate that an ensemble of classifiers, when fused over time, reduces the classification error as compared to a single classifier and static fusion of classifiers trained over the entire batch of data. The results for sliding window dynamic fusion are also provided.

We present some recent advances in concurrent and parallel programming which are promising condidates for the design and specific of hardware and in particular reconfigurable systems. We explore the relationship between parallel programming and hardware design and ask the question “are these two activities the same thing at an important level of abstraction”? In particular, we consider join patterns from join calculus, software transactional memory, futures and nested data parallel programming.

In this paper, we introduce an advanced software tool for modeling asymmetric threats, the Adaptive Safety Analysis and Monitoring (ASAM) system. The ASAM system is a hybrid model-based system for assisting intelligence analysts to identify asymmetric threats, to predict possible evolution of the suspicious activities, and to suggest strategies for countering threats. It employs a novel combination of hidden Markov models (HMMs) and Bayesian networks (BNs) to compute the likelihood that a certain threat exists. It provides a distributed processing structure for gathering, sharing, understanding, and using information to assess and predict adversary network states. We illustrate the capabilities of the ASAM system by way of application to a hypothetical model of development of nuclear weapons program by an unknown hostile country. The simulation results show that the ASAM system is able to detect the modeled pattern with a high performance (greater than 95% clutter suppression capability).

A collaboration scheme for information integration among multiple agencies (and/or various divisions within a single agency) is designed using hierarchical and hybrid Bayesian networks (HHBNs). In this scheme, raw information is represented by transactions (e.g., communication, travel, and financing) and information entities to be integrated are modeled as random variables (e.g., an event occurs, an effect exists, or an action is undertaken). Each random variable has certain states with probabilities assigned to them. Hierarchical is in terms of the model structure and hybrid stems from our usage of both general Bayesian networks (BNs) and hidden Markov models (HMMs, a special form of dynamic BNs). The general BNs are adopted in the top (decision) layer to address global assessment for a specific question (e.g., "Is target A under terrorist threat?" in the context of counterterrorism). HMMs function in the bottom (observation) layer to report processed evidence to the upper layer BN based on the local information available to a particular agency or a division. A software tool, termed the adaptive safety analysis and monitoring (ASAM) system, is developed to implement HHBNs for information integration either in a centralized or in a distributed fashion. As an example, a terrorist attack scenario gleaned from open sources is modeled and analyzed to illustrate the functionality of the proposed framework.

This paper illustrates how the synchronous programming language Esterel [3] can be used to design and verify both hardware and software. Also illustrates that power of combining these two complementary technologies for the design and verification of embedded systems. Finally we show how the Esterel technique fits into a conventional system level design flow based on Xilinx's Virtex-II PRO FPGA and present several case studies and actual demonstration of a complete system from concept to implementation.

This paper presents a way of encoding some kinds of dynamic reconfiguration behaviour in the interface portion of circuit descriptions. This has many advantages. The user of a reconfigurable circuit has some knowledge about the reconfigurable interface of the circuit. Static analysis tools can make better decisions about how to schedule virtual hardware. And most importantly the compiler can automatically synthesize the required interface between reconfigurable portions of the system and the regular portions of the design. Several existing models of dynamic reconfiguration from the literature are captured using our type system extension based on sum types. This is especially important in System-on-Chip (SoC) contexts where a reconfigurable IP block may have to communicate over a non-trivial IP bus like CoreConnect™.

"RLOC" is the name given to a relational placement macro that is used to influence the layout of circuits that are realised on FPGAs using Xilinx's place and route software. This paper explores the thesis that modern FPGA architectures are powerful enough to no longer require the designer to provide a layout and that simulated annealing technology has advanced to the point that very good results can be obtained using no layout constraints at all. If this thesis is true then there is a profound effect on custom computing machines which can be more easily targeted from high level specification languages like Handle-C and JHDL without requiring clumsy layout information to be accommodated at the language level.

Human designers have done amazing things with FPGAs. These designs challenge our assumptions about the speeds and densities acheivable by programmable hardware. But with multi-million gate designs and increasingly complex FPGA architectures is there really any place for the hand-crafted design anymore? Is there a way that CAD tools can incorporate the techniques and knowledge of designers to create high-density, high-performance implementations automatically? Or will the tools and architectures always lag the applications, thereby guaranteeing abundant job opportunities for FPGA design experts?

This report investigates how some of the new features in Xilinx's Virtex FPGA may be use to support the efficient implementation of a graphics application via a synthesis flow. The principle new features that we investigate are BlockRAM, distributed RAM, special support for multiplication and the fully digital delay-locked loop (DLL) for controlling multiple clock domains.

Testing dynamically reconfigurable systems imposes new challenges which require special treatment. We present tools and techniques we developed for debugging a dynamically reconfigurable system that performs run-time constant propagation optimisations. An application for monitoring the effect of run-time specialisation is presented and we show how we adapted standard testability techniques to evaluate the performance of specialised circuits. We also outline how NDLs that capture reconfiguration at a high level can assist with debugging.

We show how a formal verification methodology can complement conventional verification for the development of FPGA-based cores. As FPGAs become larger, there is a greater reliance on shrink-wrapped intellectual property. In particular, customers expect rigorous verification of the cores that they purchase. We report on positive experience of using formal verification to facilitate the development of real cores. We then show how formal verification has a special role to play during the dynamic reconfiguration of cores.

We describe preliminary results of dynamically specialising Xilinx XC6200 FPGA circuits using the partial evaluation method. This method provides a systematic way to manage the complexity of dynamic reconfiguration in the special case where a general circuit is specialised with respect to a slowly changing input. We describe how we address the verification and run-time support issues which are raised when one modifies a circuit at run-time.

This paper presents the results of a project designed to produce a commercial application for reconfigurable logic. We describe how we took the popular image processing application Adobe Photoshop and used its plug-in technology to devise a set of FPGA-based filters to accelerate colour space conversion and image convolution operations. Some of the barriers that make it difficult to produce portable FPGA-based filters are explored.

Lava is a tool to assist circuit designers in specifying, designing, verifying and implementing hardware. It is a collection of Haskell modules. The system design exploits functional programming language features, such as monads and type classes, to provide multiple interpretations of circuit descriptions. These interpretations implement standard circuit analyses such as simulation, formal verification and the generation of code for the production of real circuits.Lava also uses polymorphism and higher order functions to provide more abstract and general descriptions than are possible in traditional hardware description languages. Two Fast Fourier Transform circuit examples illustrate this.

The feasibility of run-time reconfiguration of FPGAs has been established by a large number of case studies. However, these systems have typically involved an ad hoc combination of hardware and software. The software that manages the dynamic reconfiguration is typically specialised to one application and one hardware configuration. We present three different applications of dynamic reconfiguration, based on research activities at Glasgow University, and extract a set of common requirements. We present the design of an extensible run-time system for managing the dynamic reconfiguration of FPGAs, motivated by these requirements. The system is called RAGE, and incorporates operating-system style services that permit sophisticated and high level operations on circuits.

Dynamic reconfiguration of FPGAs is a powerful technique for modifying a circuit as it executes. However, dynamic reconfiguration is inadequately supported by CAD tools and poorly understood in general. We present a specific class of dynamic reconfigurations that can be expressed in terms of a formalism called partial evaluation. This provides a systematic framework for understanding the effect of a dynamic reconfiguration, as well as providing guidance on how to complete specialised circuits. The primary advantages of this technique are circuits which are smaller and faster for a certain class of applications. We present one case study from the ATM field which benefits from this treatment.

FPGA-based synthesis roofs require information about behaviour and architecture to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices.