The field of neuromorphic computing is approaching an era of rapid adoption driven by the urgent need of a substitute for the von Neumann computing architecture. NEUROTEC I: “Neuro-inspired Artificial Intelligence Technologies for the Elec-tronics of the Future” project is an initiative sponsored by the German Federal Ministry of Education and Research (BMBF for its initials in German), that aims to effectively advance the foundations for the utilization and exploitation of neuromorphic computing. NEUROTEC I stands at its successful “final stage” driven by the collaboration from more than 8 institutes from the Jiilich Research Center and the RWTH Aachen University, as well as collaboration from several high-tech industry partners. The NEUROTEC I project considers the field interplay among materials, circuits, design and simulation tools. This paper provides an overview of the project's overall structure and discusses the scientific achievements of its individual activities.

Memristive devices, such as ReRAM devices, enable Computation-In-Memory operations such as vector-matrix multiplications, which are basic kernels for neuromorphic computing. These devices, however, suffer from parasitic sneak path currents in memory arrays, which make a satisfactory performance on large-scale arrays impossible. To overcome this issue, for example, a bipolar rectifying element (‘select device’) in series to a resistive switching device (1S1R) is introduced at each cross-point junction. In this work, we investigate the design of 1S1R arrays for VMM operations and show the impact of wire resistances on these operations. We derive guidelines that give a quantitative relationship between the array size, wire resistance values, resistance states of the ReRAM and the select device and resulting current levels.

As the cost of keeping Moore’s law alive is ever increasing, unconventional device and circuit concepts are being explored, both in industry and in academic research arena. Among the new devices being explored are two terminals redox-based memristive devices, which can function as both a nonvolatile memory and a computing element. For enabling Computation-in-Memory (CIM) concepts, these devices are generally integrated in a passive configuration or in an active configuration, where transistors are employed together with the memristive switches. However, the reliability and variability of the memristive devices might impact the performance of CIM circuits. In this work, we experimentally demonstrate the impact of device-to-device (D2D) and cycle-to-cycle (C2C) variability on a simple IMPLY logic gate realized in passive and active configurations. The experimental data is theoretically verified by a physics based Verilog-A model of the memristive devices. Our findings suggest that the success rate of the logic operation can be increased by exploiting the D2D variability in the memristive devices.

Computation-in-Memory (CiM) with emerging non-volatile memories leads to significant performance and energy efficiency, which is a promising approach to address so-called memory wall of conventional von Neumann architectures. Redox-based Random access memory (ReRAM) is an appropriate candidate for the realization of CiM concepts in CMOS co-integrated crossbar structures. However, ReRAM devices suffer from inherent variability in fabrication and operation. In this paper, we propose a statistical failure probability framework for the reliability evaluation of ReRAM-based CiM. Based on this, a comprehensive reliability analysis is performed for logic operations in ReRAM-based Scouting and MAGIC concepts at the crossbar level. Our proposed framework shows that existing logic operation in the crossbar architecture has a high failure probability due to the variability and crossbar non-idealities. Hence, a modified crossbar design is proposed to achieve the target reliability requirements.

In this work, TaOx based ReRAM devices were fabricated by reactive sputtering. The impact of RF power on the device characteristics was investigated using five different RF powers ranging from 116 W (RF 20%) to 356 W (RF 60%), resulting in different film deposition rates. Depending on RF power, both the initial device resistance (Rinitial) and forming voltage (Vform) were found to be changed. The switching layer sputtered at 116 W shows the highest Rinitial(80 GΩ), whereas the lowest resistance (50 kΩ) is obtained at 236 W. The device RESET level (Roff) is a function of Rinitialand Vform. The largest memory window (Roff/ Ron~ 105) and 2-bit MLC operation are achieved at 236 W deposition power. These devices show excellent retention at 125 °C for 104seconds and good endurance up to 106cycles. These results reflect the impact of the sputtering deposition power on the electrical performance of the ReRAM devices. It is due to the fact that the structural defects and oxygen content in the deposited film are modulated by the sputtering power.

In this work, we use a Cr-doped V2O3based Mott oscillator circuit to build a reservoir computing system that has much smaller model size than an equivalent LSTM. In contrast to an LSTM, our reservoir computing system can be trained very efficiently and on-line, with very low latency. We demonstrate close to state-of-the-art performance with three benchmark tasks: speech recognition, handwritten digit recognition, and HDD channel decoding. We show that our Mott circuit-based reservoir computing system brings significant reduction in power consumption and inference speed compared to CPU, GPU, or FPGA based systems.

Redox-based resistive switching devices are an emerging class of non-volatile ultra-scalable memory and logic devices. These devices offer complex internal device physics leading to rich dynamical behavior. Memristive device models are intended to reproduce the underlying redox-based resistive switching device behavior accurately to enable proper circuit simulations. A specific feature of resistively switching devices is the controllability of multi-level resistive states by using a current compliance during the SET operation. Here, we consider a one-transistor-one-resistive-switch circuit to study the multi-level capability of three different types of memristive models. The feasibility of current compliance induced multi-level resistance state control is a check for the accuracy of the memristive device model.

Memristive devices enable non-volatile data storage and in-memory computing capabilities. By using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer additional functionalities such as arithmetic operations. To enable storage and computing on large-scale arrays, parasitic current paths within the array must be avoided. Therefore, for example, a complementary resistive switch (1CRS) or a bipolar rectifying element (‘selector’) in series to a resistive switching device (1S1R) is required at each cross-point junction to suppress low-ohmic sneak paths. In this work 1S1R arrays are considered. First, the in-memory adder concept, initially developed for CRS arrays, is adjusted for a 1S1R array. After that an optimized design is presented and verified by means of memristive simulations. Third, the energy consumption of both concepts is evaluated as a function of array size, and the delay of memristive adder designs are compared quantitatively.

This paper addresses the two main resistive switching (RS) memory technologies: phase-change memory (PCM) and redox-based resistive random access memory (ReRAM). It will review the basic concepts, the initial promises, and current state of the art, with focus on possible scaling pathways for low-power operation and dense, true 3-D memory. Recent physical insights and new potential concepts will be discussed.

Integration density is a major drawback of today's associative memories required for intelligent data processing for such as pattern recognition or classification. Ultra dense complementary resistive switch-based architectures are thought to overcome this issue, offering a footprint of 4F2. Here we demonstrate the feasibility of an 8 by 16 associative capacitive network.

Highly predictive memristive models of resistive switches are required to simulate the behavior of anti-serially connected resistive switches, so called complementary resistive switches (CRSs). As an emerging non-volatile device suited for ultra-dense memory architectures, CRS cells offer great potential also as content addressable memories. Here, we introduce a circuit model for TaOx-based resistive switches which we implemented in VerilogA. This model is capable of predicting CRS behavior correctly.

Recent advancements in resistive switching cell are based on three conduction mechanisms - electrochemical (ECM), Valence-change (VCM) and thermo-chemical (TCM). In the ECM type cells, migration of anions, typically oxygen ions, towards the anode, and reduction of the cation sublattice provide either metallically or semiconducting phases and triggers a bipolar memory operation. The major factors determining the functionality of the ECM cells are the electrode reaction and the transport kinetics. The VCM type switching is generally observed in metal oxides. Finally, the resistive switching based on the TCM mechanism is discussed. Whenever, this thermo-chemical effect dominates over the electrochemical effect, a unipolar switching behavior is observed. Conductive filament formed during the electroforming process is interpreted as a sequence of threshold switching and subsequent Joule heating, which triggers local redox reactions.

In this work, we address the following question: Where do the resistive switching processes take place in memristive thin-film devices of the single crystalline model material Fe-doped SrTiO3? We compare resistive switching induced by the tip of the atomic force microscope on the bare thin-film surface with the switching properties observed in memristive devices with Pt top electrode. In order to close the gap between these two approaches, we combine conductive-tip atomic force microscopy with a delamination technique to remove the top electrode of Fe-doped SrTiO3metal-insulator-metal (MIM) structures to gain insight into the active switching interface with nanoscale lateral resolution. This enables us to prove the coexistence of a filamentary and area-dependent switching process with opposite switching polarities in the same sample. The spatially resolved analysis by transmission electron microscopy and photoelectron spectromicroscopy gives us some hints that the two switching types take place in device regions with different defect density and significant stoichiometry difference.

Many memory candidates based on beyond complementary metal-oxide-semiconductor (CMOS) nanoelectronics have been proposed, but no clear successor has yet been identified. In this paper, we offer a methodology for system-level analysis and address the relationship of the maximum performance of a given memory device type to device physics. The method is illustrated for the classical dynamic RAM (DRAM) device and for the emerging memory device known as the resistive RAM (ReRAM).