We describe in detail the parallel implementation of a family of additive lagged-Fibonacci pseudorandom number generators. The theoretical structure of these generators is exploited to preserve their well-known randomness properties and to provide a parallel system of distinct cycles. The algorithm presented here solves the reproducibility problem for a far larger class of parallel Monte Carlo applications than has been previously possible. In particular, Monte Carlo applications that undergo "splitting" can be coded to be reproducible, independent both of the number of processors and the execution order of the parallel processes. A library of portable C routines that implements these ideas is also described.>

Splash 2 is an attached parallel processor in which the computing elements are user-programmable FPGA devices. The architecture of Splash 2 is designed to accelerate the solution of problems which exhibit at least modest amounts of temporal or data parallelism. Applications are developed by writing descriptions of algorithms in VHDL, which are then iteratively refined and debugged within a simulator. Once an application is determined to be functionally correct in simulation, it is compiled to a gate list and optimized by logic synthesis. The gate list is then mapped onto the FPGA architecture by automatic placement and routing tools to form a loadable FPGA object module. A C language library and a symbolic debugger comprise the execution environment. The Splash 2 system has been shown to be effective on a variety of applications, including text searching, sequence analysis, and image processing.>

Abstract At the Supcrcomputing Research Center we have built a computing farm consisting of 16 SPARCStation. ELCs. The ELCs all support the Mother distributed shared memory, which has primitives to support efficient synchronization and use of the network and processors. Mother docs not support the traditional consistency semantics provided by, for example, Ivy or Mach external pagers. The first parallel application we ran on the farm was a Monte Carlo radiative heat transfer simulation. The performance we achieved on the farm was within an order of magnitude of the performance we would expect to achieve on a 16‐processor model of the C90 supercomputer available from Cray Research. With this application we found that the use of the Mother distributed shared memory allowed us to run the same code on the Cray as we ran on the SPARCStatlons, and we did not require the complex cache‐coherent memory semantics provided by, say, Ivy or Mach to run this application effectively.

At the Supercomputing Research Center the authors have built a compute farm consisting of 16 SPARCStation ELCs. The ELCs all support the Mether distributed shared memory, which has primitives to support efficient synchronization and use of the network and processors. The first parallel application they ran on the farm was a Monte Carlo radiative heat transfer simulation. The performance they achieved on the farm was within an order of magnitude of the performance they would expect to achieve on a 16-processor model of the C90 supercomputer available from Cray Research. With this application, they found that the use of the Mether distributed shared memory allowed them to run the same code on the Cray as they ran on the SPARCStations.>

This paper analyzes two memory hot spot problems associated with massively parallel MIMD computers.The jirst is the memory stride problem, which is similar to stride problems found in existing supercomputers.Pseudo-random interleaving, as proposed by Norton and Melton, is the preferred solution.The second hot spot problem occurs in designs that use two separate memory accesses to lock and unlock critical sections (split transaction) and employ a jirst comeljirst serve queuing mechanism for shared memory locations.A bistabilip in throughput brought about by these conditions is analyzed and experimentally demonstrated.Simple equations are presented which predict the throughput at a critical section of code as a function of the number of applied threads.These equations also express the maximum number of threads that can safely be applied without the possibility of stalling.

This paper describes an application implemented on a simulated machine called Horizon. One purpose of this study is to investigate some of the features of a possible future machine (or class of machines) with a view toward deciding, early on in the research cycle, where problems may come up, what features should be added or strengthened, and what proposed features seem to be unnecessary. Another purpose is to learn more about how to program, instrument and debug a shared memory, massively parallel MIMD computer, and to begin to answer some of the questions: What tools does a programmer need to debug this type of machine? How can a programmer know if the machine is performing well? How can bottlenecks be identified? How can the massive amount of instrumentation information be condensed and presented to a user in a way that makes sense?

A fully vectorized version of a one-dimensional Monte Carlo algorithm applied to molecular aerodynamics is presented. The algorithm is applied to the Rayleigh problem, an impulsively accelerated, heated flat plate, and is implemented on the CYBER 205. Issues relating to the details of vectorization, including the use of bit addressability, the maintaining of long vector lengths, and vector gather/scatter use, are discussed. Speedup factors due to vectorization in the range of 5 to 18 are reported, depending on problem parameters. The results indicate that under certain circumstances, the problem performs well on vector architectures.>