This paper proposes efficient trimmed-sample Monte Carlo (TSMC) methodology and novel yield-aware design flow for analog circuits. This approach focuses on "trimming simulation samples" to speedup MC analysis. The best possible yield and the worst performance are provided "before" MC simulations such that designers can stop MC analysis and start improving circuits earlier. Moreover, this work can combine with variance reduction techniques or low discrepancy sequences to reduce the MC simulation cost further. Using Latin Hypercube Sampling as an example, this approach gives 29x to 54x speedup over traditional MC analysis and the yield estimation errors are all smaller than 1%. For analog system designs, the proposed flow is still efficient for high-level MC analysis, as demonstrated by a PLL system.

In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, this article proposes a fast heuristic approach that tries to finish all iteration steps of the yield enhancement flow at behavior level. First, a novel force-directed Nominal Point Moving (NPM) algorithm is proposed to find a better nominal point without building the feasible regions. Then, an equation-based behavior-level sizing approach is proposed to map the NPM results at performance level to behavior-level parameters. A fast behavior-level Monte Carlo simulation is also proposed to shorten the iterative yield enhancement flow. Finally, using the obtained behavioral parameters as the sizing targets of each subblock, the device sizing time is significantly reduced instead of sizing from the system-level specifications directly. As demonstrated on several analog circuits, this heuristic approach could be another efficient methodology to help designers improve their analog circuits toward better yield.

In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, this work tries to finish all iteration steps of the yield enhancement flow at behavior level. First, a novel force-directed nominal point moving (NPM) algorithm is proposed to find a better nominal point without building the feasible regions. Then, an equation-based behavior-level sizing approach is proposed to map the NPM results at performance level to behavior-level parameters. A fast behavior-level Monte Carlo simulation is also proposed to shorten the iterative yield enhancement flow. Finally, using the obtained behavioral parameters as the sizing targets of each sub-block, the device sizing time is significantly reduced instead of sizing from the system-level specifications directly. As demonstrated on a complex CPPLL design, this behavior-level approach could be another efficient methodology to help designers improve their analog circuits toward better yield.

Using behavioral models to perform fast simulation is currently a popular solution to verify SOC designs. Previous analog behavior modeling approaches often treat the noisy VDDwaveform as a given input and focus on reflecting such stimuli on circuit performance. However, because the interaction of noise aggressors and victims is not considered, some errors may exist in the simulation. In this paper, a simple SCORE macromodel is proposed for PLL designs. It can be integrated with a supply-noise-aware PLL behavioral model to analyze supply noise effects at high level. In addition to numerical results, the time-varying supply noise waveform and real-time PLL responses can be obtained simultaneously. As demonstrated in the experimental results, the proposed approach can provide more realistic simulation results with noise interaction effects but still keep fast simulation time.

Using behavioral models to perform system simulation at behavioral level is currently a popular solution to verify SOC designs. For analog behavioral models, most of previous approaches are developed with the assumption that noise waveforms are known functions, such as sinusoid waves or Gaussian noise. However, while co-simulated with other blocks in the system, the actual supply noise induced by other circuits is often very irregular and unpredictable. Therefore, the simulation results may still have some errors in real environment. In this paper, an efficient behavioral modeling approach for PLL designs is proposed to analyze the real-time supply noise effects. Instead of directly modeling the final circuit performance as a single complicated equation, we try to model suitable intermediate parameters whose relationship to supply noise is much simpler. The experimental results have shown that our approach can accurately deal with irregular noise with such a simple model

In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL circuits more quickly by using Verilog-AMS language. Not only top-down applications but also bottom-up applications can be supported by using our PLL models. The main idea is to use a special "characterization mode" to get critical circuit parameters. In the characterization mode, only two input patterns are enough to get circuit properties with parasitic effects. In the experimental results, we will build an accurate PLL behavioral models for demonstration compared to the HSPICE results and typical behavioral models.