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Yuan-Chieh Hsu

dblp:31/471 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.022001
Path delay fault diagnosis in combinational circuits with implicitfault enumeration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits · IEEE Trans. Computers 1996
Electronic design automation › hardware verification and test › fault diagnosis › logic diagnosis
delay fault diagnosis
0.012001
Path delay fault diagnosis in combinational circuits with implicitfault enumeration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Electronic design automation › hardware verification and test › delay fault testing
path delay fault
0.012001
Path delay fault diagnosis in combinational circuits with implicitfault enumeration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Electronic design automation › hardware verification and test
delay fault testing
0.011996
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits · IEEE Trans. Computers 1996
Electronic design automation › hardware verification and test
fault simulation
0.011996
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits · IEEE Trans. Computers 1996
Electronic design automation › hardware verification and test
fault diagnosis
0.012001
Path delay fault diagnosis in combinational circuits with implicitfault enumeration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Electronic design automation › hardware test
test coverage
0.011996
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits · IEEE Trans. Computers 1996

Methods — techniques the papers use, named apart from their topics

implicit fault enumeration · 0.0effect-cause analysis · 0.0
YearPublicationVenuePosition
2001 Path delay fault diagnosis in combinational circuits with implicitfault enumeration
abstract
A new methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. The paper illustrates a structural representation, called the suspect circuit, of all the possible path delay faults in a faulty circuit. This representation has been used to design efficient algorithms that enable us to manipulate the suspect faults without having to enumerate them explicitly. Procedures for removing fault-free paths from the list of suspect faults have been implemented to improve the diagnostic resolution. Moreover, efficient data structures are used to complement the procedures and reduce the memory footprint of the algorithms. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.
Pankaj Pant, Yuan-Chieh Hsu, Sandeep Gupta 0001, Abhijit Chatterjee
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1998 An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing
abstract
At-speed robust path delay testing is more desirable than the commonly employed slow-fast delay testing due to lower test application time, lower area overhead, and increased possibility of detecting unmodeled faults that cause errors only during at-speed circuit operation. However, it has been observed in practice that at-speed application of tests generated by existing test generators can lead to their invalidation. In this paper, we first present techniques to modify tests generated by existing test generators to avoid invalidation during at-speed testing. We then present a new procedure to generate tests suitable for at-speed delay testing of combinational circuits. Experimental results show that (a) at-speed application of test sets generated by existing generators leads to significant test invalidation, where the degree of invalidation is approximately proportional to the degree of compactness of the test set, and (b) the at-speed robust path delay tests generated by the proposed test generator are significantly shorter than those obtained by modifying the tests generated by existing generators.
Yuan-Chieh Hsu, Sandeep Gupta 0001
Asian Test Symposium1
1998 A new path-oriented effect-cause methodology to diagnose delay failures
abstract
A new methodology to diagnose delay failures is described. Key characteristics of the methodology are: (a) path-oriented diagnosis, (b) effect-cause reasoning, and (c) utilization of information obtained from the passing vectors. Two new representations are developed to make manageable the complexity of a path-oriented methodology. The results of diagnosis are: (a) proven to include all possible causes of observed delay errors, and (b) empirically found to have very high resolution.
Yuan-Chieh Hsu, Sandeep Gupta 0001
ITC1
1996 A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits
abstract
Conditions are derived for robust testing of a path delay fault via a sequence of vectors applied at-speed. A simulator has been developed that uses the above conditions, along with the knowledge of paths that are robustly tested by the previous vectors, to determine the fault coverage obtained by such testing. The results demonstrate that the existing fault simulators can overestimate robust path delay fault coverage by 5-15%.
Yuan-Chieh Hsu, Sandeep Gupta 0001
IEEE Trans. Computers1