Energy management has become one of the great challenges in portable computing. This is the result of the increasing energy requirements of modern portable devices without a corresponding increase in battery technology. uSleep is an energy reduction technique for handheld devices that is most effective when the handheld's processor is lightly loaded, such as when the user is reading a document or looking at a web page. When possible, rather than using the processor's idle mode, uSleep tries to put the processor in sleep mode for short periods (less than one second) without affecting the user's experience. To enhance the perception that the system is on, an image is maintained on the display and activity is resumed as a result of external events such as touch-screen and button activity. We have implemented, analyzed and evaluated uSleep on a prototype pocket computer, where it has reduced energy consumption by up to 60%.

Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries.>

A systolic array of dedicated processing elements (PEs) is presented as the heart of a multimodel of several widely-used neural models, including multilayer perceptrons with the backpropagation learning rule and Kohonen feature maps. Each PE holds an element of the synaptic weight matrix. An instantaneous swapping mechanism of the weight matrix allows the implementation of neural networks larger than the physical PE array. A systolically-flowing instruction accompanies each input vector propagating in the array. This avoids the need of emptying and refilling the array when the operating mode of the array is changed. Both the GENES-IV chip, containing a matrix of 2 /spl times/ 2 PEs, and an auxiliary arithmetic circuit have been manufactured and successfully tested. The MANTRA I machine has been built around these chips. Peak performances of the full system are between 200 and 400 MCPS in the evolution phase and between 100 and 200 MCUPS during the learning phase (depending on the algorithm being implemented).>

K2 is a distributed-memory parallel processor designed to support a multi-user, multi-tasking, time-sharing operating system and an automatically parallelizing FORTRAN compiler. This paper presents the architecture and the hardware implementation of K2, and focuses on the architectural features required by the operating system and the compiler. A prototype machine with 24 processors is currently being developed.