EDBT 2026 Demo / reviewers in the wild / expert
Nisha Talagala
dblp:31/5164
· DBLP profile ↗
9ranked-venue papers
0as first author
1since 2021 · last 2024
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7Databases, data management, data science and information retrieval · 2Artificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Storage systems · 63% Memory systems · 27% Cloud and datacenter computing · 11% | |
| Databases, data mining, and information retrieval
1 paper |
Machine learning and data management · 100% | |
| Software engineering, system software, and programming languages
2 papers |
Software maintenance and evolution · 60% Operating systems · 40% |
Topics — the 12 heaviest of 14, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
flash and SSD |
0.4 | 2 | 2014 | Snapshots in a flash with ioSnap · EuroSys 2014 Write policies for host-side flash caches · FAST 2013 |
Memory systems
non-volatile memory |
0.3 | 2 | 2015 | ANViL: Advanced Virtualization for Modern Non-Volatile Memory Devices · FAST 2015 NVMKV: A Scalable, Lightweight, FTL-aware Key-Value Store · USENIX ATC 2015 |
Storage systems › flash and SSD › flash memory management
flash translation layer |
0.3 | 2 | 2015 | Snapshots in a flash with ioSnap · EuroSys 2014 NVMKV: A Scalable, Lightweight, FTL-aware Key-Value Store · USENIX ATC 2015 |
Storage systems › key-value storage
flash-based key-value store |
0.2 | 1 | 2015 | NVMKV: A Scalable, Lightweight, FTL-aware Key-Value Store · USENIX ATC 2015 |
Storage systems
key-value storage |
0.2 | 1 | 2015 | NVMKV: A Scalable, Lightweight, FTL-aware Key-Value Store · USENIX ATC 2015 |
Cloud and datacenter computing
virtualization |
0.2 | 1 | 2015 | ANViL: Advanced Virtualization for Modern Non-Volatile Memory Devices · FAST 2015 |
Storage systems › file systems
snapshot |
0.2 | 1 | 2014 | Snapshots in a flash with ioSnap · EuroSys 2014 |
Memory systems › cache design
write policy |
0.2 | 1 | 2013 | Write policies for host-side flash caches · FAST 2013 |
Operating systems › resource management
memory management |
0.1 | 1 | 2015 | ANViL: Advanced Virtualization for Modern Non-Volatile Memory Devices · FAST 2015 |
Storage systems
storage reliability |
0.1 | 1 | 2014 | Snapshots in a flash with ioSnap · EuroSys 2014 |
Memory systems
cache |
0.0 | 1 | 2013 | Write policies for host-side flash caches · FAST 2013 |
Memory systems › cache management › storage caching › caching policy
cache write policy |
0.0 | 1 | 2013 | Write policies for host-side flash caches · FAST 2013 |
Methods — techniques the papers use, named apart from their topics
FTL-aware key-value store · 0.2flash-oriented optimization · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Advanced ML Approaches to PGx Recommendations in Precision MedicineabstractWe present a machine learning model to predict pharmacogenetic (PGx) guidelines using a novel dataset assembled from the PharmGKB knowledge base, incorporating chemical structure, genetic information and recommendation annotations. To facilitate modeling, free text recommendations were processed via domain expertise assisted NLP to create three categories: Standard Dose, Adjusted Dose, and Alternate Drug. We compared several models including Multi-Layer Perceptron, K Nearest Neighbors, Random Forest, Logistic Regression, Linear SVC, and XGBoost. XGBoost excelled, combining predictive power with explainability, achieving an accuracy of 89.14% and F1 scores from 0.85-0.90, with precision and recall of 0.83-0.97 and 0.82-0.97 respectively. Such models can accelerate PGx guidelines, enhancing personalized medicine in clinical settings. Michael Zastrozhin, Danika Gupta, Nisha Talagala, Jason Akram, Roman Grachev, Allan Gobbs, Nasreen Karaf, Alex Timoshenko |
COMPSAC | 3 |
| 2018 | Interpretability and Reproducability in Production Machine Learning ApplicationsabstractExplainability/Interpretability in machine learning applications is becoming critical, with legal and industry requirements demanding human understandable machine learning results. We describe the additional complexities that occur when a known interpretability technique (canary models) is applied to a real production scenario. We furthermore argue that reproducibility is a key feature in practical usages of such interpretability techniques in production scenarios. With this motivation, we present a production ML reproducibility solution, namely a comprehensive time ordered event sequence for machine learning applications. We demonstrate how our approach can bring this known common interpretability technique into production viability. We further present the system design and early performance characteristics of our reproducibility solution. Sindhu Ghanta, Sriram Subramanian, Swaminathan Sundararaman, Lior Khermosh, Vinay Sridhar, Dulcardo Arteaga, Qianmei Luo, Dhananjoy Das, Nisha Talagala |
ICMLA | 9 |
| 2018 | Model Governance: Reducing the Anarchy of Production ML
Vinay Sridhar, Sriram Subramanian, Dulcardo Arteaga, Swaminathan Sundararaman, Drew S. Roselli, Nisha Talagala |
USENIX ATC | 6 |
| 2015 | ANViL: Advanced Virtualization for Modern Non-Volatile Memory Devices
Zev Weiss, Sriram Subramanian, Swaminathan Sundararaman, Nisha Talagala, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau |
FAST | 4 |
| 2015 | NVMKV: A Scalable, Lightweight, FTL-aware Key-Value Store
Leonardo Mármol, Swaminathan Sundararaman, Nisha Talagala, Raju Rangaswami |
USENIX ATC | 3 |
| 2014 | Snapshots in a flash with ioSnapabstractSnapshots are a common and heavily relied upon feature in storage systems. The high performance of flash-based storage systems brings new, more stringent, requirements for this classic capability. We present ioSnap, a flash optimized snapshot system. Through careful design exploiting common snapshot usage patterns and flash oriented optimizations, including leveraging native characteristics of Flash Translation Layers, ioSnap delivers low-overhead snapshots with minimal disruption to foreground traffic. Through our evaluation, we show that ioSnap incurs negligible performance overhead during normal operation, and that common-case operations such as snapshot creation and deletion incur little cost. We also demonstrate techniques to mitigate the performance impact on foreground I/O during intensive snapshot operations such as activation. Overall, ioSnap represents a case study of how to integrate snapshots into a modern, well-engineered flash-based storage system. Sriram Subramanian, Swaminathan Sundararaman, Nisha Talagala, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau |
EuroSys | 3 |
| 2014 | NVMKV: A Scalable and Lightweight Flash Aware Key-Value Store
Leonardo Mármol, Swaminathan Sundararaman, Nisha Talagala, Raju Rangaswami, Sushma Devendrappa, Bharath Ramsundar, Sriram Ganesan |
HotStorage | 3 |
| 2013 | Write policies for host-side flash caches
Ricardo Koller, Leonardo Mármol, Raju Rangaswami, Swaminathan Sundararaman, Nisha Talagala, Ming Zhao 0002 |
FAST | 5 |
| 2013 | HEC: improving endurance of high performance flash-based cache devicesabstractFlash memory is widely used for its fast random I/O access performance in a gamut of enterprise storage applications. However, due to the limited endurance and asymmetric write performance of flash memory, minimizing writes to a flash device is critical for both performance and endurance. Previous studies have focused on flash memory as a candidate for primary storage devices; little is known about its behavior as a Solid State Cache (SSC) device. In this paper, we propose HEC, a High Endurance Cache that aims to improve overall device endurance via reduced media writes and erases while maximizing cache hit rate performance. We analyze the added write pressures that cache workloads place on flash devices and propose optimizations at both the cache and flash management layers to improve endurance while maintaining or increasing cache hit rate. We demonstrate the individual and cumulative contributions of cache admission policy, cache eviction policy, flash garbage collection policy, and flash device configuration on a) hit rate, b) overall writes, and c) erases as seen by the SSC device. Through our improved cache and flash optimizations, 83% of the analyzed workload ensembles achieved increased or maintained hit rate with write reductions up to 20x, and erase count reductions up to 6x. Jingpei Yang, Ned Plasson, Greg Gillis, Nisha Talagala |
SYSTOR | 4 |