Demo Data from EDBT 2026 / reviewers in the wild / expert
Szu-Yu Chen
dblp:31/5217
· DBLP profile ↗
7ranked-venue papers
2as first author
2since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 1 first-authorArtificial intelligence and machine learning · 2 · 1 first-author · 2 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.2 | 2 | 2012 | Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation
design for manufacturability |
0.1 | 1 | 2012 | Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Electronic design automation › physical design › lithography
double patterning lithography |
0.1 | 1 | 2012 | Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Electronic design automation › physical design › lithography
layout decomposition |
0.1 | 1 | 2012 | Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Electronic design automation › physical design
lithography |
0.1 | 1 | 2012 | Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Electronic design automation › physical design › routing › steiner tree construction
obstacle-avoiding rectilinear steiner minimum tree |
0.1 | 1 | 2008 | Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation › physical design
routing |
0.1 | 1 | 2008 | Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation › physical design › layout optimization
wire length minimization |
0.0 | 1 | 2008 | Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Methods — techniques the papers use, named apart from their topics
wire perturbation · 0.1geometry-based prediction · 0.11-d compaction · 0.1steiner point insertion · 0.1spanning graph · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | An Effective Strategy for Modeling Score Ordinality and Non-uniform Intervals in Automated Speaking AssessmentabstractA recent line of research on automated speaking assessment (ASA) has benefited from self-supervised learning (SSL) representations, which capture rich acoustic and linguistic patterns in non-native speech without underlying assumptions of feature curation. However, speech-based SSL models capture acoustic-related traits but overlook linguistic content, while text-based SSL models rely on ASR output and fail to encode prosodic nuances. Moreover, most prior arts treat proficiency levels as nominal classes, ignoring their ordinal structure and non-uniform intervals between proficiency labels. To address these limitations, we propose an effective ASA approach combining SSL with handcrafted indicator features via a novel modeling paradigm. We further introduce a multi-margin ordinal loss that jointly models both the score ordinality and non-uniform intervals of proficiency labels. Extensive experiments on the TEEMI corpus show that our method consistently outperforms strong baselines and generalizes well to unseen prompts. Tien-Hong Lo, Szu-Yu Chen, Yao-Ting Sung, Berlin Chen |
ASRU | 2 |
| 2024 | TEEMI: a speaking practice tool for L2 English learners
Szu-Yu Chen, Tien-Hong Lo, Yao-Ting Sung, Ching-Yu Tseng, Berlin Chen |
INTERSPEECH | 1 |
| 2012 | Cell segmentation and NC ratio analysis of third harmonic generation virtual biopsy images based on marker-controlled gradient watershed algorithmabstractTraditional biopsy procedure requires invasive tissue removal from a living subject followed by time-consuming complicatedly processing, so noninvasive in vivo virtual biopsy is a highly desired technique which own ability to obtain exhaustive tissue images without removing tissues from subjects. Some sets of in vivo virtual biopsy images provided by some healthy volunteers are processed by our cell segmentation approach based on marker-controlled gradient watershed algorithm to isolate the nuclei and cytoplasm and also evaluate their Nuclear-to-Cytoplasmic (NC) ratio. From our experimental results, our algorithm has significant potential for in vivo cell segmentation and NC ratio analysis to identify or detect the early symptoms of some skin diseases with abnormal NC ratios, such as skin cancers in clinical diagnosis. Huan-Hsiang Lin, Ming-Rung Tsai, Chun-Fu Chen 0001, Szu-Yu Chen, Yi-Hua Liao, Gwo Giun Lee, Chi-Kuang Sun |
ISCAS | 4 |
| 2012 | Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning TechnologyabstractDouble patterning technology (DPT), in which a dense layout pattern is decomposed into two separate masks to relax its pitch, is the most popular lithography solution for the sub-22 nm node to enhance pattern printability. Previous work focused on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NCs) which cannot be resolved by any kind of stitch insertion. A design with NCs is not DPT-compliant and may fail the decomposition, resulting in design for manufacturability redesign and longer design cycles. In this paper, we give a sufficient condition for the NC existence and propose a geometry-based method for NC prediction to develop an early-stage analyzer for DPT decomposability checking. Then, a wire perturbation algorithm is presented to fix as many NCs in the layout as possible. The algorithm is based on iterative 1-D compaction and can easily be embedded into existing industrial compaction systems. The algorithm is then further applied to further reduce the number of stitches required for the decomposition process. Experimental results show that the proposed algorithm can significantly reduce the number of NCs by an average of 85% and reduce the number of stitches by an average of 39%, which may effectively increase the decomposition success rate for the next stage. Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2010 | Native-conflict-aware wire perturbation for double patterning technologyabstractThe double patterning technology (DPT), in which a dense layout pattern is decomposed into two separate masks to relax its pitch, is the most popular lithography solution for the sub-22nm node to enhance pattern printability. Previous works focus on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NC's) which cannot be resolved by any kind of stitch insertion. A design with NC's is not DPT-compliance and will eventually fail the decomposition, resulting in DFM redesign and longer design cycles. In this paper, we give a sufficient condition for the NC existence and propose a geometry-based method for NC prediction to develop an early stage analyzer for DPT decomposability checking. Then, a wire perturbation algorithm is presented to fix as many NC's in the layout as possible. The algorithm is based on iterative 1D-compaction and can easily be embedded into existing industrial compaction systems. Experimental results show that the proposed algorithm can significantly reduce the number of NC's by an average of 85%, which can effectively increase the decomposition success rate for the next stage. Szu-Yu Chen, Yao-Wen Chang |
ICCAD | 1 |
| 2008 | Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning GraphsabstractGiven a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph, this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any two-pin net and many higher pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works. Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2007 | Efficient obstacle-avoiding rectilinear steiner tree constructionabstractGiven a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph (OASG), this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any 2-pin net and many higher-pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works. Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang |
ISPD | 2 |