This IP session will consist of three presentations. A summary of each presentation is given below.

Chiplet-based designs enable the heterogeneous integration of die from multiple process nodes into a single packaged product. High-bandwidth memory is a well-known high-volume chiplet-based product. Today, most chiplet-based logic products are single-vendor products built with proprietary die-to-die (D2D) interfaces between the chiplets in a package. Industry and academia have developed standards and methods to address the test challenges expected with chiplet-based products. These efforts have focused on improving die yield and test access structures. The Open Compute Project’s Open Domain-Specific Architecture (ODSA) is a new effort that aims to define an open physical and logical D2D interface and create a marketplace of chiplets. With an open interface, product developers can integrate best in class chiplets from multiple vendors. An open D2D interface offers both new opportunities and challenges in testing multi-chiplet products. The opportunity is in leveraging economies of scale. The challenge is in enabling greater interoperability between test structures in different chiplets and across vendors. This paper reviews recent developments in chiplet test, especially leveraging work on HBM and discusses their extension to testing products based on open D2D interfaces.

In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the ompression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduces the computation time to find a solution for partial LFSR reseeding. Experimental results on ISCAS89 benchmark circuits show that our approach is better than either dictionary coding or LFSR reseeding, and outperforms several test data compression methods proposed recently.

For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this paper we first study the reason for strong correlation between Iddq currents for different test vectors, then build a model to estimate the correlation. Based on this model, we propose three test vector selection methods to improve the fault detection ability of ratio-Iddq testing by selecting test vector pairs with the highest correlation. Hspice simulation showed that the fault detection ability can be improved by as much as an order of magnitude. We also describe a test vector partitioning technique to increase the correlation between Iddq currents of different test vectors.

Dynamic Idd test methods have been shown to detect defects that escape other test techniques. Normal process variations decrease the fault coverage and affect the performance of dynamic Idd test techniques. A dynamic-current based test metric, Energy Consumption Ratio (ECR), has been proposed to address the process variation problem and has been validated through extensive simulations and applications on manufactured circuits. In this paper, we first discuss the problems in practical implementation of ECR tests on large-size circuits of advanced technology, e.g., increased circuit size and leakage current degrade ECR performance. We then propose two possible solutions: one is based on extensive statistical data analysis and another uses an enhanced scan design to partition the circuit. Experimental results from simulations and actual devices are included in this paper.

Dynamic I/sub dd/ techniques can potentially address the limitations of traditional test techniques and the Idd, test. Normal process variations in manufacturing affect dynamic Idd techniques in two ways. Since a fault-free circuit can produce a range of responses, they necessitate the use of a threshold-based test process. Process variations also degrade the resolution and consequently the fault coverage of a test technique. The authors develop statistical techniques to set thresholds in a dynamic Idd test process. The techniques use Principal Component Analysis, a statistical analysis technique,. to identify process corners and compute statistical models. Our techniques are applied to average current-based dynamic tests and to tests based on the energy consumption ratio (ECR). The ECR is a new test metric which offers several advantages, including tolerance to process variations, over other dynamic test techniques. The authors demonstrate that their techniques lead to computationally efficient methods to set accurate thresholds without either significant yield or fault coverage loss. To the best of their knowledge, this is the first systematic technique to set thresholds for a dynamic I/sub dd/ test method.

Undesired capacitive crosstalk between signals is expected to be a significant concern in deep submicron circuits. New test techniques are needed for these crosstalk faults since they may cause unacceptable performance degradation. We analyze the impact of crosstalk faults on a circuit's power dissipation. Crosstalk faults can be detected by monitoring the dynamic supply current. The test method is based on a recently developed dynamic I/sub dd/ test metric, the energy consumption ratio (ECR). ECR-based test has been shown to be effective at tolerating the impact of process variations. In this paper, we apply an ECR-based test method called ECR-VDD test to detect the crosstalk faults. The effectiveness of the method is demonstrated by simulation results.

Parallel simulation on multiple processors is one method by which fault simulation time in large circuits can be reduced significantly. To realize near-linear execution time gains from parallel processing, the parallelization techniques used should result in an even computational load distribution across the processors in the parallel system. Fault simulation can be parallelized either by partitioning the set of faults, the set of vectors or both. We develop a fault partitioning technique for parallel simulation. The technique is applied to a commercial fault simulator from IBM. Most previous efforts at multiprocessor fault simulation have been validated on small publicly-available benchmark circuits. Our methods are validated on a large circuit with over a million faults. Our partitioning techniques result in a uniform load distribution on this circuit over a range of partitions, from one with 4 blocks to one with 12 blocks. In each case, the partitioning technique is quantifiably superior to random partitioning, by an order of magnitude. We also develop techniques to effectively combine fault-parallel arid vector-parallel multiprocessor simulation. This combined approach results in better execution time when compared to using each approach individually.

A recently developed dynamic I/sub dd/ test parameter, the Energy Consumption Ratio (ECR), is based on the average current drawn by a circuit. Very fast measurement equipment is needed to measure the exact supply current transients in high-speed circuits. However, the ECR requires the average value of the transient supply current and not the exact transient. Common sampling and filtering techniques can be combined to greatly reduce measurement cost. Three approaches to combine filtering and different sampling techniques are studied in this paper. Theoretical analysis based on first order approximation and simulation results for these approaches are also presented.

As tester complexity and cost increase, reducing test time is an important manufacturing priority. Test time can be reduced by ordering tests so as to fail defective units early in the test process. Algorithms to order tests that guarantee optimality require execution time that is exponential in the number of tests applied. We develop a simple polynomial-time heuristic to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. An ordering algorithm requires information on the ability of tests to detect defective units. One way to obtain this information is by simulation. We obtain it by applying all possible tests to a small subset of manufactured units and assuming the information obtained from this subset is representative. The ordering heuristic was applied to manufactured digital and analog integrated circuits (ICs) tested with commercial testers. When both approaches work, the orders generated by the heuristic are optimal. More importantly, the heuristic is able to generate an improved order for large problem sizes when the optimal algorithm is not able to do so. The new test orders result in a significant reduction, as high as a factor of four, in the time needed to identify defective units. We also assess the validity of using such sampling techniques to order tests.

The functional performance of switched capacitor circuits is directly affected by variations in capacitor ratios. We have proposed techniques to accurately measure these capacitor ratios. In this paper we develop an optimal procedure to minimize the number of capacitor ratios that need to be measured while still maintaining the desired fault coverage. We make use of the sensitivity of individual performance specifications to specific capacitor ratios. The procedure has been validated with a number of examples including a first order lossy integrator a second order low-pass filter and sixth order high Q bandpass filter. The procedure developed in this paper can easily be extended to include other switched capacitor circuits.

Built-in self-test (BIST) schemes need to set the state of the circuit under test (CUT) for each test vector applied. The two primary techniques by which the state is set are test-per-scan and test-per-clock. In a test-per-scan scheme, circuit states are set using one or more scan chains. Several scan cycles are required to apply a single test vector. In very large circuits, the time to apply each test vector may be quite high. The direct option of reducing test time with a fast scan clock is difficult to realize in practice. In a test-per-clock scheme, all circuit flip-flops are loaded in parallel. A new test vector can be applied in each cycle. The area overhead incurred in accessing each storage element directly is quite significant. We propose a new Broadcast BIST (B/sup 2/IST) scheme as a compromise between the two approaches. B/sup 2/IST uses time-division multiplexing (TDM) to load multiple storage elements in a broadcast group in a single clock cycle, but through only a single scan data input. Based on our B/sup 2/IST simulation, we compare the layout overhead and performance of B/sup 2/IST with that of traditional BIST schemes on ISCAS benchmark circuits. Thus, B/sup 2/IST can achieve the performance of a test-per-clock scheme, but only incur the overhead of a test-per-scan scheme.

An analysis of the energy consumption ratio (ECR) test method, based on simulation study of resistive bridges and resistive opens, is presented. These defect classes comprise a very significant percentage of the defects causing speed failures. We show: (i) bridges causing delay failures and detectable by the difference I/sub DDQ/ method is detected by the ECR test method; and (ii) bridges and opens causing delay failures but not detectable by the difference I/sub DDQ/ method are also detected by the ECR test method. This highlights a very significant advantage of the ECR test method over I/sub DDQ/ test methods. The underlying reason as to why the ECR test method is good at detecting delay defects is presented. Based on that we develop a new test method called the ECR-VDD test. The usefulness of the new method in detecting delay defects is validated using simulation results.

Dynamic current-based test techniques can potentially address the drawbacks of traditional and I/sub ddq/ test methodologies. The quality of dynamic current-based test is degraded by process variations in integrated circuit (IC) manufacture. The energy consumption ratio (ECR) is a new metric that improves the effectiveness of dynamic current test by reducing the impact of process variations by an order of magnitude. In this paper, we address issues that are of practical importance to an ECR-based test methodology. We use the ECR to test a low-voltage submicron IC with a microprocessor core. The ECR more than doubles the effectiveness of the dynamic current test already used to test the IC. The defect coverage of the ECR is greater than that offered by any other test, including I/sub ddq/. We develop a logic-level fault simulation tool for the ECR. We also show that statistical techniques can be used to set thresholds for an ECR-based test process. Our results demonstrate that the ECR offers several advantages relative to other transient current-based test methods and to I/sub ddq/ test. The ECR offers the potential to be a high quality low cost test methodology.

Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature.

Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration it is used in.We present a DFT scheme that offers the accuracy needed to test high-quality circuits.The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors.The circuit is used to completely characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios.In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy, and filter parameters can be shown to be satisfied to within 0.1% accuracy.A filter can be shown to satisfy all its functional specifications through this characterization process.We believe the accuracy of our scheme is at least an order of magnitude greater than that offered by any other scheme reported in the literature.

Dynamic-current based test techniques can potentially address the drawbacks of traditional and I ddq test methodologies.The quality of dynamic current based test is degraded by process variations in IC manufacture.The energy consumption ratio (ECR) is a new metric that improves the effectiveness of dynamic current test by reducing the impact of process variations by an order of magnitude.We address several issues of significant practical importance to an ECR-based test methodology.We use the ECR to test a low-voltage submicron IC with a microprocessor core.The ECR more than doubles the effectiveness of the dynamic current test already used to test the IC.The fault coverage of the ECR is greater than that offered by any other test, including I ddq .We develop a logic-level fault simulation tool for the ECR and techniques to set the threshold for an ECR-based test process.Our results demonstrate that the ECR offers the potential to be a high-quality low-cost test methodology.To the best of our knowledge, this is the first dynamic-current based test technique to be validated with manufactured ICs.

Advances in technology and increasing integration are expected to degrade the effectiveness of I/sub ddq/ test. Total leakage currents per IC are expected to be very large, making it difficult to detect the impact of a single defect (T.W. Williams et al., 1996; M. Sachdev, 1997). Test methods which detect faults by monitoring the dynamic supply current have been suggested as one alternative. Almost all the dynamic current techniques proposed in the literature are adversely affected by the impact of process variations. Many are also susceptible to timing and magnitude errors in measurement. The energy consumption ratio (ECR) is a new dynamic current-based test metric (B. Vinnakota et al., 1998), that addresses some of these problems. ECR-based test offers several advantages over other dynamic test methods and the I/sub ddq/ test such as tolerance to process variations, reduced test process complexity and a proven ability to detect faults that escape other techniques. The ECR has been validated through extensive simulation and through application to a 50K gate sub-micron biomedical IC (W. Jiang and B. Vinnakota, 1999). Our contributions are directed towards further validating the real quality of the ECR.

Process variations degrade the resolution and consequently the fault coverage of I/sub dd/ test techniques. We develop statistical techniques to set thresholds in a dynamic I/sub dd/ test process. The techniques use principal component analysis to identify process corners and compute statistical models. Our techniques are applied to average current-based dynamic test and to test based on the energy consumption ratio. We demonstrate that our techniques lead to computationally efficient methods to set accurate thresholds without either significant yield or fault coverage loss. To the best of our knowledge, this is the first systematic technique to set thresholds for a dynamic I/sub dd/ test method.

Test time can be reduced by ordering tests so as to fail defective units early in the test process. An ordering algorithm requires information on the ability of tests to detect defective units. We obtain it by applying all possible tests to a small subset of manufactured units and assume the information obtained from this sub-set is representative. We develop a simple polynomial-time heuristic which uses the information from the sample set to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. Optimal test ordering algorithms require execution time which is exponential in the number of tests applied. In our experiments, the heuristic results in a significant reduction in test time for manufactured digital and analog ICs.

Fault simulation is a computer-intensive problem. Parallel processing is one method to reduce simulation time. In this paper, we discuss a technique to partition the fault set for fault-parallel simulation on multiple processors. When applied statically, the technique can scale well for up to 32 processors. The fault-set partitioning technique is simple and can itself be parallelized. Existing uniprocessor algorithms, based on parallel-pattern simulation, can be used for multiprocessor simulation without modification. Therefore, the techniques can be used effectively on a low-cost parallel resource such as a network of workstations.

Unique input/output(UIO) sequences are used for state verification and functional test in finite state machines. A UIO sequence for a state s distinguishes it from other states in the FSM. Current algorithms to compute UIO sequences are limited in their applicability to FSMs with binary input symbols such as those found in con trol applications. Execution times of traditional approaches are exponential in the n umber of FSM inputs. We dev elop a new heuristic algorithm to generate UIO sequences for FSMs with binary inputs. Execution time is reduced significantly b y reducing the size of the search space. When a UIO sequence cannot be generated, our algorithm generates a small n umber of functional faults for state verification.

We develop a new technique for fault detection based on a new metric, the energy consumption ratio (ECR). ECR-based test can detect faults, such as redundant faults, that escape detection with other techniques. Though the ECR is a metric based on the supply current, an analog parameter, it is remarkably tolerant to the impact of process variations. The quality of ECR-based test is demonstrated through extensive simulation on a process offered by MOSIS. We also present a test generation algorithm for the new test technique. When applied to benchmark circuits, this technique reliably detects a large fraction of the combinationally redundant faults in them.

Test generator algorithms may be classified by the level of circuit description they utilize. Algorithms based on a logic-gate level description of the circuit under test (CUT) are the most common. Functional algorithms utilize a functional description of the CUT. Functional test generation techniques may provide better defect coverages than do purely logic-level techniques. Multilevel test generation algorithms attempt to realize the advantages of both approaches by utilizing fault translation. Here, gate-level faults are translated to functional faults and test generation is performed at the functional level. In this paper, we develop and present new techniques for fast efficient fault translation from the logic to the functional level. These techniques are implemented in a multilevel sequential circuit test generation system. The performance of the system is investigated on benchmark circuits.

We present a new multiprocessor sequential circuit fault simulator, Zamlog, based on a novel uniprocessor simulator, Zambezi. Both the fault and test sets are partitioned for multiprocessor simulation. The parallelization technique, designed to preserve the efficiency of Zambezi, is simple to implement and has low communication requirements. Experimental results indicate that Zamlog can obtain speedups of up to 95. The speedups obtained and the scalability are between 3 and 10 times better than any reported in the literature. Furthermore, the speed-ups obtained are with respect to a uniprocessor algorithm which is superior, by an average of 40%, to those used to gauge the speed-ups of previous parallel systems.

Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control flow, of existing parallel pattern algorithms. For a very wide range of benchmark circuits, compared to parallel fault and parallel pattern simulators, ZAMBEZI offers either the best, or very close to the best, uniprocessor performance. ZAMBEZI also offers superior performance when parallelized.

In this paper, we suggest that the dynamic power dissipation of a circuit can be used to detect faults in it. The change in dissipation caused by a fault can be maximized by applying specific test vectors. For example circuits, we show that the power dissipation can be used to detect faults which do not affect static power dissipation. We also discuss how faults may be detected with a frequency domain analysis. In many cases, the Fourier spectra of the power supply currents in the good and faulty circuits will be very different. Power monitoring is also verified experimentally, for an example circuit.

{ Analog IC test occupies a signi cant fraction of the design cycle.Testing costs are increased by the twin requirements of high precision and accuracy in signal measurement.We discuss a system level ACOB technique for fully dierential analog ICs.Our test techniques incorporate analog speci c constraints such as device matching, and circuit and switching noise.They have a minimal impact on performance, area and power.The techniques can be used for both discrete and continuous time circuits, over a wide frequency range.The system level DFT scheme is also used to design a self-testing switched capacitor lter.Our checking scheme provides signi cant fault coverage and is demonstrably superior to other DFT techniques for dierential circuits.

Fault simulation is a compute intensive problem. Data parallel simulation on multiple processors is one method to reduce fault simulation time. We discuss a novel technique to partition the fault set for data parallel fault simulation. When applied statically, the technique can scale well for up to eight processors. The fault set partitioning technique is simple, can itself be parallelized, and can be implemented with extreme ease. Therefore, the technique can be used on a low cost parallel resource, such as a network of workstations.

We present new methods to reduce test times in sequential circuits using scan. The problem of reducing test application time is shown to be computationally intractable. We discuss heuristic techniques to reduce test times. Fault simulation and correlation between test vectors are used to reduce test times, without affecting fault coverage. Our methods can be used to process a test set after test generation is complete. They lead to a substantial reduction in test times.

In look-up table-based multiplication schemes, techniques based on tables of squares require less memory than techniques based on direct implementations. In this paper, we present a method to realize an n-bit multiplier using a table of squares for n-bit integers. A new technique to store tables of squares is also presented. The new scheme is shown to compare favorably, in terms of storage requirements, with a scheme wherein the entire table of squares is stored directly. The addressing requirements of the new storage technique are also discussed.>

Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques.Functional TPG algorithms utilize a functional description of a circuit.Multilevel TPG algorithms attempt to realize the advantages of both approaches through fault translation.In such systems, gate-level faults are translated to functional faults and TPG is performed at the functional level.We develop and present new techniques for fast ecient fault translation from the logic to the functional level.These techniques are implemented in a m ulti-level sequential circuit test generation system.Performance results for benchmark circuits are presented. 31

In addition to the traditional problems associated with testing ICs, analog circuit test is very susceptible to measurement induced errors. Precise calibration and signal matching are necessary to minimize these errors. These constraints increase the complexity and cost of analog circuit testers. In this paper, we introduce analog circuit observer blocks (ACOBs). ACOBs are designed to simplify test result observation in analog and mixed-signal ICs. Measurement errors are minimized since ACOBs are better matched to the circuits being tested and impose a lower load as well. If successful, they can reduce tester complexity. We present designs for ACOBs for a fully differential operational amplifier and a pipelined A/D converter.>

A simple method to determine the Reed-Muller canonical expansion is described. This method is based on array processing techniques similar to those used for the FFT. A specific advantage of the technique is that it can be used with minor modification to determine the expansion when some or all of the input variables are negated.>

Algorithm-based fault tolerance (ABPT) is a low-overhead system-level concurrent error detection and fault location scheme for multiprocessor systems. We present new methods for the design of ABFT systems. Our design procedure is applicable to a wide range of systems in which processors share data elements. A feature of our design approach is that the type of checks to be used in the final system can be controlled by the system designer. We also present some new bounds on the number of checks needed in ABFT system design.>

In this paper, the design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers which used carry-propagate adders/subtractors. These dividers are slow because of their O(W/sup 2/) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two's-complement form is shown to be not C-testable. It is modified to be linear-testable (in word-length) instead of exponential time required for exhaustive testing of all possible combinations at its inputs. We conclude that the number of test vectors needed is 99 for C-testing of the divider array and (3W+10) for linear testing of the converter. The hardware overhead required to make the divider C-testable and the on-the-fly converter linear testable is also shown to be nominal.>

The design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and modified to make it C-testable, i.e. it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers that used carry-propagate adders/subtractors. These dividers are slow because of their O(W/sup 2/) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two's-complement form is shown not to be C-testable. It is modified to be linear-testable (in word-length), instead of taking the exponential time required for exhaustively testing all possible combinations at its inputs.>

Parallel processing architectures are commonly used for signal processing and other computationally intensive applications. These applications are characterized by high throughput and long processing periods. Such characteristics decrease the reliability of high-performance architectures. The erroneous data produced by faulty processors could have damaging consequences, particularly in critical real-time applications. It is therefore desirable that any erroneous data produced by the system be detected and located as quickly as possible. Algorithm-based fault tolerance (ABFT) is a low-cost system-level concurrent error detection and fault location scheme. Methods used in the analysis of multiprocessor systems using system-level diagnosis are applied to the analysis of ABFT systems. A new algorithm for analyzing an ABFT system for its fault diagnosability is developed using these methods. Based on this work, a fault diagnosis algorithm is developed for ABFT systems.>

Algorithm-based fault tolerance (ABFT) is a method for improving the reliability of parallel architectures used for computation-intensive tasks. A two-stage approach to the synthesis of ABFT systems is proposed. In the first stage, a system-level code is chosen to encode the data used in the algorithm. In the second stage, the optimal architecture to implement the scheme is chosen using dependence graphs. Dependence graphs are a graph-theoretic form of algorithm representation. The authors demonstrate that not all architectures are ideal for the implementation of a particular ABFT scheme. They propose new measures to characterize the fault tolerance capability of a system to better exploit the proposed synthesis method. Dependence graphs can also be used for the synthesis of ABFT schemes for non-linear problems. An example of a fault-tolerant median filter is provided to illustrate their utility for such problems.>

A graph-theoretic formulation for memory repair in the presence of clustered faults is presented. This approach is based on the use of variable-cell-size grids (VCS grids). As VCS grids can be represented by bipartite graphs, the reconfiguration problem for clustered faults can also be formulated as a vertex covering problem. Hence, graph-based reconfiguration algorithms developed by previous authors can be extended to exploit clustered fault distributions. Algorithms for memory repair that do not suffer from the restrictions imposed by previous algorithms for clustered faults are developed. A heuristic repair algorithm that has both improved performance and lower execution time than previous repair algorithms is presented.>