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M. N. Jayram

dblp:31/5361 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Embedded and real-time systems · 33%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › design representation
behavioral modeling
0.012003
A complexity effective communication model for behavioral modeling of signal processing applications · DAC 2003
Embedded and real-time systems › real-time operating systems
intertask communication
0.012003
A complexity effective communication model for behavioral modeling of signal processing applications · DAC 2003
Electronic design automation
system-level design
0.012003
A complexity effective communication model for behavioral modeling of signal processing applications · DAC 2003
YearPublicationVenuePosition
2003 A complexity effective communication model for behavioral modeling of signal processing applications
abstract
In this paper, we argue that the address space of memory regions that participate in inter task communication is over-specified by the traditional communication models used in behavioral modeling, resulting in sub-optimal implementations. We propose shared messaging communication model and the associated channels for efficient inter task communication of high bandwidth data streams in behavioral models of signal processing applications. In shared messaging model, tasks communicate data through special memory regions whose address space is unspecified by the model without introducing non determinism. Address space to these regions can be assigned during mapping of application to specific architecture, by exploring feasible alternatives. We present experimental results to show that this flexibility reduces the complexity (e.g., communication latency, memory usage) of implementations significantly (up to an order of magnitude).
M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy 0001
DAC2