Stochastic computing is a promising technique for realizing high-performance computing owing to its extremely low hardware cost. However, the stochastic number (SN) has too many information redundancies, which leads to an exponential growth of latency. So, hybrid stochastic number (HSN) is proposed to solve the high-latency problem. Hybrid stochastic computing technology brings latency and efficiency advantages but faces the rigorous challenges of bit-width accumulation. In this study, a recoding method with high accuracy for HSN is proposed to reduce the bit width of HSN with only one clock delay. The hardware-resource savings in the polynomial circuit reach more than 80%. Then, the accuracy and fault tolerance of recoding are evaluated. The recoding method enables the pipeline structure in the pure HSN domain, preventing data conversion at the midpoint of the computation. Furthermore, based on the recoding method, a low-cost, bit-flip correction method for HSN is proposed, for realizing fault-tolerant data transmission and computation.

In this article, a signed-digit hybrid stochastic number (SD-HSN), which combines the two-line bipolar stochastic number (TLB-SN) and the binary signed-digit (BSD) number, is proposed and discussed. As a bipolar format hybrid stochastic number (SN), SD-HSN extends the concept of conventional TLB-SN to a signed-digit stochastic stream. The positional-weight-based TLB-SNs are still a stochastic stream with BSD, which is computed according to the arithmetic of its expectation with the redundant number method. The multiplication by SD-HSN shows a high-computational performance thanks to the redundant SD-HSN circuit. The efficient multiply-accumulate (MAC) is implemented by SD-HSN designs with low area and low-power consumption. The fault tolerance mechanism of SD-HSN is demonstrated by a JPEG image compression algorithm and a neural network. Besides, SD-HSN shows its advantage in hardware cost and power consumption over conventional BSD number multiplication and its high accuracy, high efficiency, and low latency compared to the classic stochastic computing (SC) methods. The SD-HSN circuits proposed, which include a generator, adder, and multiplier, are designed and implemented based on a standard 40-nm CMOS process.

Stochastic computing (SC) is unique in that it is a type of arithmetic computation based on stochastic numbers (bitstream) instead of binary numbers (BNs). Stochastic number (SN) represents and carries information in the form of pseudo-analog probabilities by CMOS gate circuits. The renewed success of the stochastic number system is mainly related to super low power consumption and high reliability for edge computing. In fact, the stochastic number is a nonpositional number representation that is intrinsically sequential and consequently used for certain important arithmetic operations (such as addition/subtraction and multiplication), and corresponds to a super low area circuit. This article proposes a novel hybrid number system of BNs and stochastic number representation, called hybrid stochastic number (HSN). This study introduces the basic theoretical aspects of the HSN and demonstrates the properties of hybrid stochastic computing (HSC). The hardware implementation of deep neural network with HSC is fabricated using a standard 40-nm low-power CMOS process, with a core area of 0.53 mm2, power of 102.3 mW, and clock of 400 MHz, which has 4544 multiply accumulation operations (MACs).

Stochastic computing (SC) is a type of logic computation that converts binary numbers to stochastic bitstream. It is a pseudo-analog computation in the digital domain that can realize multiplication, addition and complex function computations. In this paper, we present a new encoding method AFE(Amplitude and Frequency Encoding) for SC, which extend SC to use multibit streams instead of bit streams to represent data. This new method still use the expectation of streams to achieve the computation. Compared with conventional stochastic bitstream, AFE SC proposed realize low-latency and low-area occupation instead of the long latency of classic method. And we also discuss the rationality of circuits from a mathematical perspective. The hardware logic circuits of AFE-SC including multiplier, adder and converter are designed and implemented by FPGA. In addition, the latency of computing, area and precision of AFE-SC is measured based on FPGA board.

Stochastic computing (SC) is a type of logic computation based on stochastic bit stream instead of the binary numbers (BNs). It is pseudo-analog computation in the digital domain that can realize multiplication, addition, and complex function computations. In this brief, a new encoding method, referred to as amplitude and frequency encoding (AFE) for SC, is presented. It extends SC to use multibit streams instead of bit streams to represent data. This method still uses the expectation of streams to achieve computation. Compared with the conventional stochastic bit stream, AFE realizes low-latency and low-area occupation than the conventional SC method. The rationality of the circuits is also examined from a mathematical perspective. The hardware logic circuit of AFE SC, including the multiplier, adder, and converter, was designed and implemented by a field-programmable gate array (FPGA). In addition, the latency of the computing, area, and precision of AFE SC was measured based on the FPGA board.

In this paper, we introduce a binary neural network accelerator which using a new binarization method and hardware sparse. We propose the weights and the activations to either 1 or 0 instead of +1 or −1, which makes the convolution process simplified and more suitable for hardware implementation. To decrease the data access from off-chip memory, we propose a novel data reuse method, which can reduce 58.8% data access, while the weight isolation logic is designed to reduce power consumption. Based on the weight isolation and the retiming technique, the proposed BNN accelerator achieves low power consumption at 500MHz clock by the VC709 Evaluation Kit. Experimental results show that the proposed accelerator achieves a throughput of 3378 GOPS and 1624 GOPS/W energy efficiency.

The paper proposes an 8-bit AMOLED driver IC with a polynomial interpolation DAC. This architecture maintains high-accuracy AMOLED panels with 8-bit compensated gamma correction and supporting low-complex configuration which results in additional occupied die area. The proposed driver consists of a 6-bit gamma correction resistor-string DAC and a 2-bit polynomial interpolation current-modulation sub-DAC. The two-stage DAC leads to a compact die size compared with conventional 8-bit resister-string DAC, and the polynomial interpolation method provides high accurate grey level voltages than linear one. The AMOLED driver was realized in 0.35-μm CMOS process with DNL and INL of 0.43 LSB and 0.43 LSB.

The self-connection can enlarge the memory capacity of an associative memory based on the neural network, however, the basin size of the embedded memory state shrinks. The problem of basin size is related to undesirable stable states which are spurious states. If we can destabilize these spurious states, we expect to improve the basin size. The inverse function delayed (ID) model which includes the BVP model has the negative resistance on its dynamics. The negative resistance of the ID model can destabilize the equilibrium states on some regions of conventional neural network. Hence, the associative memory based on the ID model has possibilities of improving the basin size of the network which has the self-connection in order to enlarge a memory capacity. In this paper, we show the improvement of performance compared with the conventional neural network by computer simulation.