As the process technology advances, reducing the leakage power as much as possible is one of the utmost challenging tasks in chip implementation. Utilizing cells with multi-VT (threshold voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, for the sequential cells on the timing critical paths in circuits, there is no easy way for the multi-VT method to reduce the leakage power unless timing is not sacrificed. To overcome this barrier, we introduce a set of new standard cells called hybrid-VT flipflop cells, each of which is implemented with two different VT types, one implanted onto its master latch while the other onto its slave latch, by which the setup time and clock-to-Q delay can be controlled individually and independently. We confirm that applying our power recovery method utilizing hybrid-VT flipflop cells to the benchmark circuits, which have already been optimized by the conventional multi-VT cells, is able to further reduce the leakage power by 8.97% with no timing degradation.

In multiple input switching (MIS) analysis, input signal alignment is one of the key factors which determines the quality and the accuracy of the approach. In this paper, we propose a new signal alignment methodology for MIS analysis based on a transistor level simulator at the core of the static timing analysis. Our proposed methodology searches through the possible input vectors in an efficient order to reduce the number of simulations and finds a true worst case signal alignment for both the MIN and the MAX analysis. In our 180 nm simulation setup, the worst-case delay is predicted within 0.5% error for more than 97% of test cases performing an average of less than two simulations per logic gate.

Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future technology nodes, especially for timing critical applications. This paper proposes an on-chip variability sensor using phase-locked loop (PLL) to detect process, supply voltage (VDD), and temperature variations (process, voltage, and temperature variation) or even temporal reliability degradation stemming from negative bias temperature instability. Our analysis shows that control voltage (Vcnt) of voltage-controlled oscillator in PLL can be used as a dynamic performance signature of an operating IC. Along with the proposed PLL-based sensor circuit, we also propose a variation-resilient system technique using adaptive body biasing (ABB). The PLLVcntsignal is efficiently transformed to an optimal body bias signal for various circuit blocks to avoid possible timing failures. Correspondingly, circuits can be designed with significantly relaxed timing constraint compared to conventional approaches, where a large amount of design resources can be wasted to take care of the worst-case situations. We demonstrated our approach on a test chip fabricated in IBM 130-nm CMOS technology. Measurement results show that the PLL-based sensor is cable of tracking various sources of circuit variations. Optimization analysis shows that 42% and 43% reduction in area and power can be obtained using our approach compared to the worst-case sizing. The proposed study refers to our previous study introduced in with major improvements in measurement results and analysis.

Low-temperature polycrystalline-silicon thin-film transistor (LTPS TFT) has emerged as one of the promising candidates for low-power low-cost applications on flexible substrates. In this paper, we propose a statistical simulation methodology to estimate parametric variations in scaled LTPS TFT due to the inherent properties [such as the number, location, and orientation of grain boundaries (GBs)] of the polycrystalline material. Our simulation technique employs the response surface method (RSM) to consider multiple process parameters which affect the performance distribution of LTPS TFT devices/circuits. Simulation results show that inherent GB variations result in multimodal delay distributions in basic logic building blocks (inv, nand, and nor) in scaled LTPS TFT technology, contrary to unimodal distributions in conventional bulk CMOS technology. We also observed that with increasing logic depth, the multimodal distribution converges to a unimodal distribution. Hence, to ensure robust and stable functionality of TFT technology under inherent process variations, we propose a multifinger (MF) design technique to improve the reliability of TFT circuits and to reduce the impact of GB-induced variations on TFT performance. Simulation results obtained from a 20-stage inverter chain show that by applying the proposed MF-based design, one can achieve 28% and 61% reductions in delay variations using two- and four-finger structures, respectively.

This paper evaluates the severity of negative bias temperature instability (NBTI) degradation in two major circuit applications: random logic and memory array. For improved lifetime stability, we propose/select an efficient reliability-aware circuit design methodologies. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. As a result, simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memory shows much severe effect especially when combined with the impact of random process variation, NBTI can dramatically reduce the READ stability of memory cells. Hence, aggressive design techniques such as stand-by VDD scaling or adaptive body biasing (ABB) are required in memory application to minimize the impact of NBTI.

Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characterize and estimate the lifetime circuit reliability under NBTI degradation. Unlike conventional approaches, where a representative fMAX (maximum operating frequency) measurement from timing critical circuitry is used, we propose to utilize the standby circuit leakage IDDQ as a metric to detect and characterize temporal NBTI degradation in digital circuits. Compared to the fMAX based approach, the proposed IDDQ based technique benefits from lower test cost and improved capability of estimating reliability of complex circuitries such as ALUs and SRAM arrays. We have derived an analytical expression for circuit IDDQ from the analytical PMOS Vt degradation model (ΔVt ∝ t1/6). The proposed model is verified with measurement data obtained from a test chip fabricated in 130nm technology. Furthermore, we examine the possible applications of our proposed IDDQ based NBTI characterization. We show that the temporal degradation in static noise margin (SNM) of SRAM array and fMAX of random logic circuits are highly correlated to the IDDQ measurement, and this relationship can be used to predict long term circuit reliability.

This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize on-chip phase locked loop (PLL) as a sensor to detect process, VDD, and temperature (PVT) variations or even temporal degradation stemming from negative bias temperature instability (NBTI). We will show that control voltage (Vcnt) of voltage controlled oscillator (VCO) in PLL can dynamically capture performance variations in circuit. By utilizing the Vcnt signal of PLL, we propose variation resilient circuit design using adaptive body bias (VR-ABB). Vcnt is used to generate an optimal body bias for various circuit blocks in order to avoid possible timing failures. Correspondingly, circuits can be designed with a significantly relaxed timing constraint compared to the conventional approaches, where a large amount of design resources can be wasted to take care of the worst case situations. We have demonstrated our approach using an 8 bit ripple carry adder (RCA) as an example circuit. Results show that even under extreme variations, reasonable parametric yield can be maintained while minimizing other design resources such as area and power.

We propose a design and optimization methodology for high performance and ultra low power digital applications on flexible substrate using low temperature polycrystalline silicon thin film transistor (LTPS TFT). We show that by using ultra-thin bodies and minimizing the mid-gap trap density by hydrogenation, LTPS TFTs (in 200 nm technology) can achieve higher performance than standard TFTs. We also demonstrate that it can be a promising candidate for both sub-threshold and super-threshold operation with performances comparable to contemporary bulk silicon. However, due to grain boundaries (GBs), there can be large intrinsic variations in such devices. Hence, there is a need for GB-tolerant design. Integration of proposed digital electronics in conjunction with conventional display application of LTPS TFTs on flexible substrates (system-on-panel) will open up plethora of new and interesting applications.

Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability concerns in sub- 100nm technologies. So far, studies of NBTI and its impact on circuit performance have assumed an average behavior of the degradation process. However, in very short channel devices, finite number of Si-H bonds in the channel can induce a statistical random variation of the degradation process. This results in significant random Vtvariations in PMOS transistor. The NBTI induced variation depends on operating temperature and the effective stress period for the specific device. In this paper, we analyze the impact of stochastic temporal NBTI variations and propose a compact circuit level Vtmodel. Using the proposed model, we show how temporal Vtvariations can affect the lifetime performance of different circuit topologies including 6T SRAM cell and random combinational logic circuits.

One of the major reliability concerns in nano-scale VLSI design is the time dependent Negative Bias Temperature Instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T SRAM array topology. Using an empirical NBTI model based on the reaction diffusion (RD) framework, we first examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include 1) static noise margin (SNM), 2) statistical READ&WRITE stability, and 3) standby leakage current (IDDQ). We show that due to NBTI, read stability of SRAM cell degrades, while write stability and standby leakage improve with time. Furthermore, using specific time trend of IDDQ degradation, we proposed efficient characterization technique to predict the lifetime behavior of SRAM array under NBTI.

One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative-bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage ($V_{t}$) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. An analytical expression for the time-dependent$V_{t}$degradation in PMOS transistors based on the empirical reaction-diffusion (RD) framework was employed for our analysis. Using the RD-based$V_{t}$model, we analytically examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include the following: 1) static noise margin; 2) statisticalreadandwritestability; 3) parametric yield; and 4) standby leakage current$(I_{\rm DDQ})$. We show that due to NBTI,readstability of SRAM cell degrades, whilewritestability and standby leakage improve with time. Furthermore, by carefully examining the degradation in leakage current due to NBTI, it is possible to characterize and predict the lifetime behavior of NBTI degradation in real circuit operation.

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years

Dual-Vtdesign technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different leakage components (subthreshold, gate and junction tunneling) to become significant portion of total power dissipation in CMOS circuits. High-Vtdevices are expected to have high junction tunneling current (due to stronger halo doping) compared to low-Vtdevices, which in the worst case can increase the total leakage in dual-Vtdesign. Moreover, process parameter variations (and in turn Vtvariations) are expected to be significantly high in sub-50-nm technology regime, which can severely affect the yield. In this paper, we propose a device aware simultaneous sizing and dual-Vtdesign methodology that considers each component of leakage and the impact of process variation (on both delay and leakage power) to minimize the total leakage while ensuring a target yield. Our results show that conventional dual-Vtdesign can overestimate leakage savings by 36% while incurring 17% average yield loss in 50-nm predictive technology. The proposed scheme results in 10%-20% extra leakage power savings compared to conventional dual-Vtdesign, while ensuring target yield. This paper also shows that nonscalability of the present way of realizing high-Vtdevices results in negligible power savings beyond 25-nm technology. Hence, different dual-Vtprocess options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-Vtdesigns in future technologies.

Negative Bias Temperature Instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years.

Temporal performance degradation in VLSI circuits due to Negative Bias Temperature Instability (NBTI) has emerged as a challenging design issue in nano-scale technology. In this paper, we analyze the impact of NBTI degradation in circuit performance in terms of timing, and show that under worst case scenario, one can expect more than a 10% degradation in the maximum circuit delay after 3 years (~ 108seconds) operation time. Based on this observation, we propose an efficient transistor-level sizing algorithm based on a modified Lagrangian Relaxation (LR) technique to account for the temporal degradation of circuit and guarantee lifetime reliability of circuit under NBTI. The technique reformulates the sizing problem by considering the fact that only the rising (0 → 1) delays of CMOS logic gates are affected by the NBTI. Experimental results on several ISCAS'85 benchmarks have shown that our proposed transistor-level sizing approach can reduce the area overhead of conventional cell-level sizing method by an average of 43%.

Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this article, we propose a new algorithm for statistical static timing analysis (SSTA) using levelized covariance propagation (LCP). The algorithm simultaneously considers the effect of die-to-die variations in process parameters as well as within-die variation, including systematic and random variations. In order to efficiently handle complicated process variation models while contending with the arbitrary correlation among timing signals, we employ a compact form of the levelized statistical data structure. Furthermore, we propose two enhancements to the LCP algorithms to the make it practical for the analysis of large sized circuits. Results on several ISCAS'85 benchmark circuits in predictive 70nm technology show an average of 0.19% and 0.57% errors in the mean and standard deviation, respectively, of timing analysis using the proposed technique, as compared to the Monte Carlo-based approach.

Variability in process parameters is making accurate timing analysis of nanoscale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for statistical timing analysis using levelized covariance propagation (LCP). The algorithm simultaneously considers the impact of random placement of dopants (which makes every transistor in a die independent in terms of threshold voltage) and the spatial correlation of the process parameters such as channel length, transistor width and oxide thickness due to the intra-die variations. It also considers the signal correlation due to reconvergent paths in the circuit. Results on several benchmark circuits in 70 nm technology show an average of 0.21 % and 1.07 % errors in mean and the standard deviation, respectively, in timing analysis using the proposed technique compared to the Monte-Carlo analysis.

In this paper we propose an accurate estimation and modeling of total circuit leakage distribution, considering both inter- and intra-die variations (variation in L, T/sub ox/ and random dopant fluctuation). Since, the total leakage in a circuit depends on leakage in a transistor, integration of transistors in a logic gate, and the gate topology in a circuit block, we model the total circuit leakage distribution at all levels of circuit design, while taking the different correlations among transistors, logic gates, circuit topology, and input vectors into account. The proposed model accurately estimates both statistical information (mean and variance) and the shape of the leakage distribution. We have verified the model using Monte Carlo simulation using devices of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on individual components of total leakage.

This paper explores the effectiveness of dual-V/sub t/ design under aggressive scaling of technology, which results in significant increase in all components of leakage (subthreshold, gate and junction tunneling) while having large variations in process parameters. The present way of realizing high-V/sub t/ devices results in high junction tunneling leakage compared to low-V/sub t/, devices, which in turn may result in negligible leakage savings for dual-V/sub t/, designs in scaled technologies. Moreover, increase in process variation severely affects the yield of such designs. This paper suggests important measures that need to be incorporated in conventional dual-V/sub t/, design to achieve total leakage power improvement while ensuring yield. It also shows that different process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual- V/sub t/ designs in sub-50nm technologies.

The inter-die and intra-die variations in process parameters result in large number of failures in an SRAM array degrading the design yield. In this paper, we propose an adaptive repairing technique for SRAM based on leakage and delay monitoring. Leakage and delay monitoring is used to effectively separate dies with different inter-die Vts from each other. Using the leakage (or delay) monitoring and adaptive body bias, we propose a reliable and self-repairing SRAM which has reduced number of parametric failures under high inter-die and intra-die Vt variations. The proposed self-repairing SRAM improves the design yield by 5%-40% in predictive 70nm technology from BPTM.