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EDBT 2026 Demo / reviewers in the wild / expert

Richard L. Norton

dblp:31/600 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1983
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction set architecture		 0.011983
Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets · ISCA 1983
Processor architecture and microarchitecture › instruction set architecture
RISC		 0.011983
Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets · ISCA 1983
Compilers and program optimization › compiler-hardware co-design
instruction set design		 0.011983
Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets · ISCA 1983

Methods — techniques the papers use, named apart from their topics

architectural performance analysis · 0.0
YearPublicationVenuePosition
1983 Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets
abstract
In this paper we concentrate on the effect of instruction set architecture on the performance potential of a computer system. These issues are key in considerations of what instruction set is most appropriate for the support of high level languages on general purpose machines. Two possible approaches are so called complex instruction sets, such as those of the VAX and IAPX 432, and the “reduced” instruction set of the RISC I [2] microcomputer, which is expected to have performance similar to that of a VAX 11-780.
Richard L. Norton, Jacob A. Abraham
 ISCA1
1982 Using write back cache to improve performance of multi-user multiprocessors
Richard L. Norton, Jacob A. Abraham
 ICPP1