Software-Defined Radio (SDR) represents a move from dedicated hardware to software implementations of digital communication standards. This approach offers flexibility, shorter time to market, maintainability , and lower costs, but it requires an optimized distribution tasks in order to meet performance requirements. Thus, we study the problem of scheduling SDR linear task chains of stateless and stateful tasks for streaming processing. We model this problem as a pipelined workflow scheduling problem based on pipelined and replicated parallelism on homogeneous resources. We propose an optimal dynamic programming solution and an optimal greedy algorithm named OTAC for maximizing throughput while also minimizing resource utilization . Moreover, the optimality of the proposed scheduling algorithm is proved. We evaluate our solutions and compare their execution times and schedules to other algorithms using synthetic task chains and an implementation of the DVB-S2 communication standard on the AFF3CT SDR Domain Specific Language . Our results demonstrate how OTAC quickly finds optimal schedules, leading consistently to better results than other algorithms, or equivalent results with fewer resources.

The use of high level synthesis (HLS) tools is progressing in the industrial and academic worlds as they have gained in maturity. In the last few years, they are commonly applied to design hardware accelerators for ASIC and FPGA targets. Indeed, they enable signal processing algorithm integration in a shorter amount of time than methodologies based on handmade RTL design. Moreover, suitable behavioral description facilitate design space exploration to fulfil system constraints while minimizing other parameters. In this article, HLS tool abilities to design complete signal processing systems are evaluated. To this end, a commonly used FMCW radar signal processing system is deployed. The article presents demonstrate that a large set of trade-off solutions can be produced thanks to the described models. In a second time, the interest of the proposed approach is compared to optimized multicore SIMD implementations that are also relevant to give flexibility to FMCW radar embedded systems.

An assignment algorithm is a key step for multi-object tracking. In order to guarantee real-time execution on embedded systems, it is important to choose an efficient algorithm that matches the application context and the implementation constraints. In this paper, we present a comparative study of different implementations of an auction-based assignment algorithm for asymmetric problems on a System On Module (SOM) target based on an ARM processor and an FPGA circuit. This implementation differs with previous works [1], [2] by the context of multi-object tracking on an embedded system, which implies limited assignment problems, as well as by the choice of a more efficient assignment algorithm. Parallelization strategies were applied to achieve high-efficiency levels for both hardware and software implementations. The experimental results obtained show that, first, software implementation is, in most cases, sufficient to achieve the real-time performances and secondly, that proposed implementations perform better than related work ones (~ 130x for software and ~ 1.7x for hardware).

The RISC-V open source instruction set architecture is a promising solution for applications related to low power embedded systems. This paper presents a configurable RISC-V processor architecture providing a compromise between the number of clock cycles required to execute an instruction, the maximum operating frequency, the resource utilization and the power consumption. This architectural flexibility enables the processor to be adapted to fit application constraints, on either FPGA or ASIC targets.

Summary This article presents a new Domain Specific Embedded Language (DSEL) dedicated to Software‐Defined Radio (SDR). From a set of carefully designed components, it enables to build efficient software digital communication systems, able to take advantage of the parallelism of modern processor architectures, in a straightforward and safe manner for the programmer. In particular, proposed DSEL enables the combination of pipelining and sequence duplication techniques to extract both temporal and spatial parallelism from digital communication systems. We leverage the DSEL capabilities on a real use case: a fully digital transceiver for the widely used DVB‐S2 standard designed entirely in software. Through evaluation, we show how proposed software DVB‐S2 transceiver is able to get the most from modern, high‐end multicore CPU targets.

Polar codes are a new error correction code family that should be benchmarked and evaluated in comparison to LDPC and turbo-codes. Indeed, recent advances in the 5G digital communication standard recommended the use of polar codes in EMBB control channels. However, in many cases, the implementation of efficient FEC hardware decoders is challenging. Specialised knowledge is required to enable and facilitate testing, rapid design iterations, and fast prototyping. In this article, a model-based design methodology to generate efficient hardware SC polar code decoders is presented. With HLS design process and tools, we demonstrate how FPGA system designers can quickly develop complex hardware systems with good performances. The favourable impact of design space exploration is underlined on achievable performances when a relevant computation model is used. The flexibility of the abstraction layers is evaluated. Hardware decoder generation efficiency is assessed and compared to competing approaches. It is shown that the fine-tuning of computation parallelism, bit length, pruning level, and working frequency help to design high-throughput decoders with moderate hardware complexities. Decoding throughputs higher than 300 Mbps are achieved on an Xilinx Virtex-7 device and on an Altera Stratix IV device.

Word population has almost doubled during the last century increasing dramatically the need for food to support a population over 7 billion persons. According to FAO, by 2050, the agricultural production will have to increase by 70%. Plants growth depends on several factors such as nutrients (NPK), soil characteristics, soil Ph, soil moisture, temperature, weather, and light. To manage all the required information and the complexity of plants growth a system, based on IoT technology, able to measure, analyze, and act is needed. IoT is a solution for precision agriculture. A system for precision agriculture, that will be distributed in the field, far from energy and communication sources needs to be low power and able to process the received information and just sending the most relevant information to the cloud for further statistical analysis. This system will be able to measure the most important parameters for plant growth through a set of sensors and act to fix some of those parameters through actuators when needed as well.

Cloud Radio Access Network is foreseen as one of the key features of the future 5G mobile communication standard. In this context, all the baseband processing is intended to be performed on CPUs in order to keep a high level of flexibility. The challenge is then to propose efficient software implementations of baseband processing algorithms that guarantee a sufficient throughput, while limiting the energy consumption. In this paper, as an alternative to general purpose processors, we propose an implementation of an Application Specific Instruction set Processor customized for the Successive Cancellation decoding of polar codes. The resulting software decoder achieves throughputs similar to state-of-the-art ARM processor implementations, while reducing the energy consumption by a factor 10.

The Alternate Direction Method of Multipliers (ADMM) approach is an original method for LDPC decoding based on the linear programming (LP) technique. It introduces a novelty at the error correction performance level. Nevertheless, this method can be toughly implemented due to its high computational complexity. In this paper, an implementation of the ADMM LP decoding algorithm on an FPGA target is presented. Its hardware resource cost is evaluated and compared with the state of the art LDPC decoders using the belief propagation (BP) decoding approach. The preliminary logic synthesis results show that an LP based hardware decoder for LDPC codes should be viable for applications with tough error correction requirements. However, additional research works are required to reach equivalent hardware complexity and throughput performances that are similar to traditional BP based LDPC decoders.

The enforcement of the linear programming (LP) decoding was recently extended to LDPC convolutional codes (LDPC-CC). It was demonstrated that their convolutional structure suites the message-passing based representation of the LP problem, thanks to the application of the alternating directions method of multipliers (ADMM). In this paper, a modified formulation of the ADMM-LP problem is introduced for pipeline decoding of LDPC-CCs based on the layered schedule. Moreover, an assessment of the fixed-point format required for hardware implementation is provided to evaluate the complexity of the underlying decoding algorithm. Simulations show that an 8-bit quantization scheme yields negligible error correction performances loss of about 0.05 dB regarding the floating-precision ADMM based LDPC-CC decoder. Further, an algorithmic optimization of the Euclidean projection skipping technique, described in [1] [2], is proposed. This improved version enables to reduce the computational complexity of the decoding process without memory penalty contrary to the original formulation.

Low-density parity-check convolutional codes (LDPC-CC) have interesting error correction features. They have a great potential to become a key error-correcting codes for enhancing reliability of modern digital communication systems, optical systems and storage devices. On the implementation side, however, the design of low-cost low-power and high-throughput LDPC-CC decoders remains challenging. This survey paper provides an overview of the state-of-the-art of different algorithmic optimizations proposed to ease and improve the LDPC-CC decoder implementations. To this end, a summary of the available decoding scheduling approaches is provided. Besides, a complexity analysis, performance comparison and an architectural analysis of LDPC-CC decoders based on different scheduling techniques is detailed.

Alternate direction method of multipliers (ADMM) technique has recently been proposed for LDPC decoding. Even though it improves the error rate performance compared with traditional message passing (MP) techniques, it shows a higher computation complexity. In this article, the ADMM decoding algorithm is first described. Then, its computation complexity is analyzed. Finally, an optimized version which benefits from the multi-core processors architecture as well as the ADMM algorithm s parallelism is presented. The optimized version of the ADMM decoder can achieve up to 30 Mbps for standardized LDPC codes on a laptop x86 processor. Therefore, it could guide an efficient GPU implementation for real-time and high-throughput decoding systems requiring correction performances beyond MP-Sum Product Algorithm (SPA) capabilities.

Polar coding is a new coding scheme that asymptotically achieves the capacity of several communication channels. Polar codes can be decoded with a successive cancellation (SC) decoder. In terms of hardware implementation, architectural performance of SC decoders is limited by the memory complexity. In this paper, two complementary methods are proposed to reduce the memory footprint of current state-of-the-art SC decoders. These methods must also applicable to SC-List decoders. The impacts the decoding performance in a rather negligible manner (<0.02dB), as shown by perormed simulations. The association of both methods allows a reduction of 16 ∼35% of the memory complexity for SC decoders depending on their quantization format.

In this paper, we propose a 3-phase polar codes Successive Cancellation (SC) decoder. Benefiting from the local properties of the decoding tree, 3 zones are defined and associated to 3 distinct sub-decoders. This approach reduces the memory footprint while guaranteeing a better scalability in comparison with state of the art SC decoders. Several 3-phase SC decoders are implemented on an FPGA circuit and compare favorably to state-of-the-art implementations in terms of distributed hardware resources (LUT, D-FF) and throughput. Moreover, the memory of the decoder is reduced by 37% for a N = 221polar codes.

Linear Programming (LP) is a novel technique for LDPC decoding. With the advance of the Alternate Direction Method of Multipliers (ADMM) approach, a significant step towards LP LDPC decoding scalability and optimization is made possible. Yet, this innovative decoding technique has not been implemented in hardware. Its hardware complexity has neither been estimated nor compared with traditional techniques. In this paper, an overview of the ADMM approach and its error correction performances for LDPC decoding is provided. Then, its computation complexity is evaluated to show the hardware feasibility of ADMM-based LDPC decoders. Our analysis is mainly carried at two levels. First, a quantitative complexity analysis is reported and a comparison with traditional LDPC decoders is given. Second, a proposal of a partially parallel architecture is described and its hardware complexity is evaluated then compared with state-of-the-art LDPC decoders.

Low-Density Parity-Check (LDPC) codes are an efficient way to correct transmission errors in digital communication systems. Although initially targeting strictly to ASICs due to computation complexity, LDPC decoders have been recently ported to multicore and many-core systems. Most works focused on taking advantage of GPU devices. In this paper, we propose an alternative solution based on a layered OMS/NMS LDPC decoding algorithm that can be efficiently implemented on a multi-core device using Single Instruction Multiple Data (SIMD) and Single Program Multiple Data (SPMD) programming models. Several experimentations were performed on a x86 processor target. Throughputs up to 170 Mbps were achieved on a single core of an INTEL Core i7 processor when executing 20 layered-based decoding iterations. Throughputs reaches up to 560 Mbps on four INTEL Core-i7 cores. Experimentation results show that the proposed implementations achieved similar BER correction performance than previous works. Moreover, much higher throughputs have been achieved by comparison with all previous GPU and CPU works. They range from x1.4 to x8 by comparison with recent GPU works.

Polar codes are the first error-correcting codes to provably achieve the channel capacity but with infinite code-lengths. For finite codelengths the existing decoder architectures are limited in working frequency by the partial sums computation unit. We explain in this paper how the partial sums computation can be seen as a matrix multiplication. Then, an efficient hardware implementation of this product is investigated. It has reduced logic resources and interconnections. Formalized architectures, to compute partial sums and to generate the bits of the generator matrix κ⊗n, are presented. The proposed architecture allows removing the multiplexing resources used to assigned to each processing elements the required partial sums.

In this paper, the combination of a low-complexity Multiple-input Multiple-output based on belief propagation (MIMO-BP) detector with a Non-Binary Low-Density Parity-Check (NB-LDPC) decoder is investigated. Such detection and decoding algorithms can enable an equivalent representation based on a larger Joint Factor Graph (JFG). Shuffle schedule can therefore be used jointly and simultaneously on the detector and the decoder. Actions are undertaken at the detector, decoder and the iterative receiver levels in order to reduce overall complexity. Indeed, applying the proposed low-complexity BP-based detection greatly reduces the number of operations per iteration (divided by ten), with a negligible performance penalty. EXtrinsic Information Transfer (EXIT) charts enable to analyze the convergence behaviour of the proposed iterative receiver. This analysis is used to find the best set of parameters enabling a detection-decoding process with a performance closest to the full-complexity system.

In this paper, an efficient iterative receiver for digital communication systems is investigated. It combines a Non-Binary Low-Density Parity-Check (NB-LDPC) decoder with a high-order constellation demapper and a Multiple-Input Multiple-Output (MIMO) detector. A suboptimal MIMO detector based on the Belief Propagation (BP) algorithm is investigated as an alternative to a Maximum Likelihood (ML) detector. Extrinsic information is exchanged between the detector and the decoder thanks to an iterative process. EXtrinsic Information Transfer (EXIT) charts enable to analyze the convergence behaviour of the proposed MIMO-BP detector. A suitable schedule for the different types of iterations is finally proposed to reduce the receiver latency and improve its error correction performance.

Rapid prototyping is an important step in the development and the verification of computationally demanding tasks of digital communication systems, such as Forward Error Correction (FEC) decoding. The goal is to replace time-consuming simulations based on abstract models of the system with real-time experiments under real-world conditions. GPU-like architecture is a promising approach to fully exploit the potential of FPGA-based acceleration platforms. In this article, an application-specific GPU-like architecture and a complete compilation framework for decoding LDPC codes are proposed. The interest in an application-specific GPU in comparison with current GPUs is detailed. Finally, real-time experimentations demonstrate the potential of the GPU-like decoder to investigate both algorithmic and architectural issues.

This work extends the analysis and application of a digital error correction method called Muller C-element Decoding (MCD), which has been proposed for fault masking in logic circuits comprised of unreliable elements. The proposed technique employs cascaded Muller C-elements and XOR gates to achieve efficient error-correction in the presence of internal upsets. The error-correction analysis of MCD architecture and the investigation of C-element's robustness are first introduced. We demonstrate that the MCD is able to produce error-correction benefit in a high error-rate of internal faults. Significantly, for a (3,6) short-length Low Density Parity Check (LDPC) code, when the decoding process is internally error-free the MCD achieves also a gain in terms of decoding performance by comparison to the well-known Gallager Bit-Flipping method. We further consider application of MCD to a general-purpose fault-tolerant model, coded Dual Modular Redundancy (cDMR), which offers low-redundancy error-resilience for contemporary logic systems as well as future nanoeletronic architectures.

A decoding algorithm and logic implementation is proposed for fast, low-complexity error correction in environments with a high rate of transient faults as well as hard errors. The circuit is able to correct a single error in one clock cycle, making it suitable for mitigating faults in pipelined digital logic systems. The proposed method is also resilient against internal transient gate errors that may occur within the decoder itself. In the presence of a high input error rate (0.001) and high internal gate fault rate (10-5), the new decoding algorithm is able to reduce the error probability by two orders of magnitude. An asynchronous implementation is also presented for the new algorithm, which performs iterative error-correction with reduced latency compared to synchronous algorithms.

Bit-Interleaved Coded Modulation (BICM) offers a significant improvement in error correcting performance for coded modulations over fading channels compared to the previously existing techniques. Iterative processing at the receiver side can provide additional improvement to the BICM performance. In this paper, an efficient shuffled iterative receiver is investigated for the second generation of the terrestrial digital video broadcasting standard DVB-T2. The main contribution is scheduling an efficient message passing algorithm with low latency between the demapper and the IDPC decoder. A BER performance comparison between a fixed-point version that considers architectural constraints and a theoretical version over a fading channel with erasure is presented. It validates the potential of iterative receiver as practical and competitive solution for the DVB-T2 standard.

We present in this paper a blind frame synchronization method based on the adaptation of the parity check matrix of the code. The blind synchronizer is initially based on the calculation of the log-likelihood ratios (LLR) of the syndrome elements, obtained using the parity check matrix of the code. Before applying our synchronization procedure, we propose in this paper to rearrange the parity check matrix of the code according to the reliability of the received symbols as previously introduced for decoding linear block codes with high density parity check matrix. Simulation results show that the frame error rate (FER) curves obtained after applying the proposed synchronization method to product codes are very close to the ones with perfect synchronization. In addition to its powerful synchronization properties, the main advantage of the proposed synchronization algorithm is its capability of being introduced as a part of the decoder so that no additional material is required for the synchronization step.

This paper presents an architecture design and implementation of an iterative receiver for linearly precoded MIMO systems. The receiver is composed of two main elements: an MMSE-IC equalizer and a 64-state MAX-LOG-MAP decoder which exchange soft information through an interleaving scheme. Each block of the architecture was designed to reach a trade off between complexity and error rate performance. Our objective is to validate the potential of iterative receiver as practical and competitive solution for linearly precoded MIMO systems.

The adaptive belief propagation (ABP) algorithm was recently proposed by Jiang and Narayanan for the soft decoding of Reed-Solomon (RS) codes. In this paper, simplified versions of this algorithm are investigated for the turbo decoding of product codes. The complexity of the turbo-oriented adaptive belief propagation (TAB) algorithm is significantly reduced by moving the matrix adaptation step outside of the belief propagation iteration loop. A reduced-complexity version of the TAB algorithm that offers a trade-off between performance and complexity is also proposed. Simulation results for the turbo decoding of product codes show that belief propagation based on adaptive parity check matrices is a practical alternative to the currently very popular Chase-Pyndiah algorithm.

This paper presents the implementation, on an FPGA device of an ultra high rate block turbo code decoder. First, a complexity analysis of the elementary decoder leads to a low complexity decoder architecture (area divided by 2) for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup. Based on an innovative architecture which enables the memory blocks between all half-iterations to be removed and clocked at only 37.5 MHz, the turbo decoder processes input data at 600Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmission.

This paper introduces the Modified Adaptive Belief Propagation (m-ABP) algorithm, an innovative method for the turbo decoding of product codes based on BCH component codes. The Adaptive Belief Propagation algorithm of Jiang and Narayanan is simplified by moving the matrix adaptation step outside of the iteration loop, significantly reducing the complexity. Performance in terms of the bit- error-rate (BER) of the novel turbo decoding algorithm is given. Simulation results for the turbo decoding of product codes show that compared to the Chase-Pyndiah algorithm no significant BER deviation is observed while the highly- parallelizable graph-based structure of the algorithm enables high-throughput decoding.

Interleave-division multiple access (IDMA) is a multi-user scheme in which chip interleavers are the only means of user separation. The receiver involves a chip-by-chip iterative multi-user detection. Its complexity increases in a linear manner with the number of users, the number of iterations and the number of paths in the case of multipath channels. In spite of this linear increase, this can be prohibitive if a hardware implementation of the system is expected. In this paper, we propose some reduced complexity multi-user detectors for the IDMA receiver. Performance in terms of bit error rate and complexity with respect to the number of operations of the proposed detectors are compared with that of the original detector for AWGN channels. One of the proposed detectors presents the best trade-off between performance and complexity. We then extend our study in the context of multipath channels. A system combining OFDM and IDMA using this selected detector is studied and compared with the original OFDM-IDMA system. Our results show that, for high Eb/N0, the OFDM-IDMA with the selected detector can achieve the same performance as the original one with a lower complexity.

Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage. Recently, block turbo codes using Reed-Solomon component codes have been introduced. This was motivated by the highest code rate property of Reed-Solomon codes and their efficiency for burst error correction. In fact, the main advantage of Reed-Solomon block turbo codes is for high code rate applications. For these applications, the code length and consequently the decoder complexity are smaller than for usual Bose-Chaudhuri-Hocquenghem block turbo codes. This paper presents a block turbo decoder architecture using Reed-Solomon component codes. Our elementary soft input soft output decoder is dedicated to Reed-Solomon codes (31, 29, 3) with single error correction power. To the authors' knowledge, this is the first published architecture implementing this type of decoder. Experimentation has been done on a Stratix-based NIOS development board

In this paper, we focus on the design of a communication system based on reusing IP cores. Traditional methods for designing hardware cores for this kind of applications use a RTL specification. However, they suffer from heavy limitations that prevent them from efficiently addressing the algorithmic complexity and the high flexibility required by the various application profiles. For this reason, we propose to raise the abstraction level of the specification and introduce the notion of architectural flexibility by benefiting from the emerging high-level synthesis tools. From a single behavioral-level VHDL specification, we are able to generate a variety of architectures, compliant with the most important communication standards. This technique has been successfully applied to the most important IP cores (synchronization IP, Viterbi IP and Reed-Solomon decoder IP cores) of the DVB-DSNG digital video-broadcasting standard.