Akihisa Ohta

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3ranked-venue papers

1as first author

0since 2021 · last 1998

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Reconfigurable computing and FPGAs · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Reconfigurable computing and FPGAs FPGA architecture	0.0	1	1998	A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract) · FPGA 1998
Reconfigurable computing and FPGAs › FPGA implementation FPGA datapath design	0.0	1	1998	A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract) · FPGA 1998

Year	Publication	Venue	Position
1998	FPGA for High-Performance Bit-Serial Pipeline Datapath abstract In this paper, we introduce our work on the chip design of a new FPGA chip for high-performance bit-serial pipeline datapath which is customized both in the logic architecture and routing architecture. The chip consists of 200k transistors on 3.5 mm square substrate (excluding the IO pad area) using 0.5 /spl mu/ 2-metal process technology. The estimated clock frequency is 156 MHz. Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda	ASP-DAC	3
1998	New FPGA Architecture for Bit-Serial Pipeline Datapath abstract In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems introduce large routing area overhead which is especially critical in using FPGAs, where the device utilization, and operation frequency become low because of large routing penalty. Here we propose a new FPGA architecture for high-performance bit-serial pipeline datapaths, which are very efficient in routing. Also, we refine our LUT architecture in order to efficiently implement shift registers which are required in large numbers in some bit-serial designs. Modified lookup table have two modes, combinatorial logic and shift register. Bit-serial datapath can be implemented on less number of CLBs. Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda	FCCM	1
1998	A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract) abstract No abstract available. Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda	FPGA	3