Analyzing logic masking effects in combinational circuits is an important key to evaluate soft error tolerance of circuits. Logic masking effects can be analyzed exactly with employing fault simulation. The computing complexity of a fault-simulation-based algorithm, however, is proportional to the square of circuit size, which might be unacceptable to achieve a scalable analyzer. On the other hand, a heuristic algorithm AnSER can analyze logic masking effects approximately in runtime proportional to circuit size. AnSER, however, is possible to analyze logic masking effects optimistically especially for circuits protected with spatial redundancy, which might not be suitable for soft error tolerant designs. This paper shows a robust algorithm to analyze logic masking effects pessimistically. Pessimistic analysis is guaranteed with employing the proposed algorithm, while the computing complexity of the proposed algorithm is proportional to circuit size. Experimental results show that the proposed algorithm runs about 91 times faster than a fault-simulation-based exact algorithm with 11.5% overestimate for average susceptibility to errors. For circuits partially protected with spatial redundancy, the proposed algorithm has estimated average susceptibility with 37.9% overestimates on average, while AnSER has estimated average susceptibility with 96% underestimates on average.

This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

Technology mapping for LUT-based FPGAs can be formulated as DAG covering problem that is to cover given Boolean network with a set of subgraphs called cones, which is known to be NP-hard. So far, no efficient algorithm exists to solve it exactly. Existing technology mappers employ cost flow which is a heuristic metric to indicate how good a cone is for total cost, i.e. area or power. The estimation of total cost based on cost flow might be inaccurate because it does not consider multiple fanouts adequately. This paper proposes a novel method to compute the lower bound for DAG covering problem by transforming a DAG into a tree graph. A novel mapping algorithm with weighted cost flow based on the lower bound is also presented. Weighted cost flow considers the effect of multiple fanouts accurately. Cone Resubstitution: an existing post-processing of technology mapping to reduce area/power by removing unnecessary node duplications is employed. The experimental results show that the proposed method generates networks whose average area is 7%, 7%, 10% smaller than that generated by DAOmap for K = 4, 5, 6 respectively. It is also shown that the proposed method works better than the combination of a mapper based on traditional cost flow and Cone Resubstitution. On the other hand, the proposed method generates LUT networks whose dynamic power is 10% smaller than that generated by Emap for K = 4 on average.

Recent technology mappers for LUT-based FPGAs employ cut enumeration. Although many cuts are often needed to find good network, enumerating all cuts with large size consumes run-time very much. The number of cuts exponentially increases with the size of cuts, which causes long run-time. Furthermore, an inefficiency of bottom-up merging in existing algorithms makes the run-time much longer. This paper presents a novel cut enumeration. The proposed algorithm is efficient because it enumerates cuts without bottom-up merging. Our algorithm has two modes; exhaustive enumeration and partial enumeration. Exhaustive enumeration enumerates all cuts. Partial enumeration enumerates partial cuts with a guarantee that a depth-minimum network can be constructed. The experimental results show that exhaustive enumeration runs about 3 times and 8 times faster than existing bottom-up algorithm [1] [2] for K=8, 9, respectively. The quality of network are the same. Furthermore, partial enumeration runs about 6 times and 18 times faster than bottom-up algorithm for K=8, 9, respectively. Area of network derived by the set of cuts enumerated by partial enumeration is only 4% larger than that derived by exhaustive enumeration on average, and the depth is the same.

In this paper we present the post-processing algorithm, Cut Substitution, for technology mapping for LUT-based FPGAs to minimize the area under depth minimum constraint. The problem to generate a LUT’s network whose area is minimum under depth minimum costraint seems to be as difficult as NP-Hard class problem. Cut Substitution is the process to generate a local optimum solution by eliminating redundant LUTs while the depth of network is maintained. The experiments shows that the proposed method derives the solutions whose area are 9% smaller than the solutions of a previous state-of-the-art, DAOmap on average.

We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw the patterns of circuits is a dominant factor in the manufacture time and the cost for devices. Our technique is capable of drastically reducing them by optimizing the size of characters, which are the patterns to project and are placed on CP masks. Experimental results show that our technique reduced 72.0% of EB shots in the best case, comparing with the ad hoc character sizing