Reconfigurability and low complexity are the two key requirements of finite impulse response (FIR) filters employed in multistandard wireless communication systems. In this paper, two new reconfigurable architectures of low complexity FIR filters are proposed, namely constant shifts method and programmable shifts method. The proposed FIR filter architecture is capable of operating for different wordlength filter coefficients without any overhead in the hardware circuitry. We show that dynamically reconfigurable filters can be efficiently implemented by using common subexpression elimination algorithms. The proposed architectures have been implemented and tested on Virtex 2v3000ff1152-4 field-programmable gate array and synthesized on 0.18 ¿m complementary metal-oxide-semiconductor technology with a precision of 16 bits. Design examples show that the proposed architectures offer good area and power reductions and speed improvement compared to the best existing reconfigurable FIR filter implementations in the literature.

A new approach to implement computationally efficient reconfigurable filter banks for multi-standard wireless receivers is presented in this paper. Based on the concepts of tree-structured quadrature mirror filter bank (TQMFB) and coefficient decimation approach, a reconfigurable and efficient tree-structured non-uniform filter bank (TNFB) is proposed in this paper. The proposed filter bank is designed to extract channels of non-uniform bandwidths with reduced complexity when compared to TQMFB. Each stage of the proposed filter bank consists of a modal filter and a complementary delay to obtain the low-pass and high-pass channels respectively. Design examples show that the proposed TNFB offers an average multiplication rate reduction of 69% over the TQMFB.

A new approach to implement computationally efficient reconfigurable finite impulse response (FIR) filter is presented in this paper. If the coefficients of an FIR filter are decimated by M, i.e., if every Mthcoefficient of the filter is kept unchanged and remaining coefficients are changed to zeros, a multi-band frequency response will be obtained. The resulting frequency responses will have centre frequencies at 2pik/M, where k is an integer ranging from 0 to M-1. If these multi-band frequency responses are selectively masked using inherently low complex wide transition-band masking filters, different low-pass, high-pass, bandpass, and bandstop filters can be obtained. If every Mthcoefficient is grouped together removing the zero coefficients in between, a decimated frequency response in comparison to the original frequency response is obtained. In this paper, we also show the design of a reconfigurable filter bank using the above approach.

The most computationally demanding part in the digital front-end of a Software radio receiver is the channelizer, which operates at the highest sampling rate. The channelizer extracts multiple narrowband channels from the digitized wideband input signal. The limitation of the conventional uniform Discrete Fourier transform (DFT) filter bank channelizer is that, it is incapable of extracting channels of multiple bandwidths, as the prototype filter has fixed equal bandwidths. Reconfigurable filter bank architecture for the SDR channelizer, based on multi-stage frequency response masking technique is proposed in this paper. The proposed architecture is capable of extracting channels with different bandwidths corresponding to different wireless communication standards. Design examples show that proposed architecture offers a complexity reduction of 97.2 % over the conventional Per-Channel (PC) approach and DFT filter banks.

The complexity of linear-phase finite-impulse-response (FIR) filters is dominated by the complexity of coefficient multipliers. The number of adders (subtractors) used to implement the multipliers determines the complexity of the FIR filters. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) coefficients reduce the number of adders required in the multipliers of FIR filters. A new CSE algorithm using binary representation of coefficients for the implementation of higher order FIR filters with a fewer number of adders than CSD-based CSE methods is presented in this paper. We show that the CSE method is more efficient in reducing the number of adders needed to realize the multipliers when the filter coefficients are represented in the binary form. Our observation is that the number of unpaired bits (bits that do not form CSs) is considerably few for binary coefficients compared to CSD coefficients, particularly for higher order FIR filters. As a result, the proposed binary-coefficient-based CSE method offers good reduction in the number of adders in realizing higher order filters. The reduction of adders is achieved without much increase in critical path length of filter coefficient multipliers. Design examples of FIR filters show that our method offers an average adder reduction of 18% over the best known CSE method, without any increase in the logic depth.

The most computationally demanding block in the digital front end of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Reconfigurability and low complexity are the two key requirements of the SDR channelizers. An architecture for implementing low complexity and reconfigurable finite impulse response (FIR) filters for channelizers is proposed in this paper. Our method is based on the binary common subexpression elimination (BCSE) algorithm. The proposed architecture guarantees minimum number of additions at the adder level and also at the full adder (FA) level for realizing each adder needed to implement the coefficient multipliers. The proposed architecture has been synthesized on 0.18μm CMOS technology. The synthesis results show that the proposed reconfigurable FIR filter can operate at high speed consuming minimum area and power. The average reductions in area and power are found to be 49% and 46% respectively with an average increase in speed of operation of 35% compared to other reconfigurable FIR filter architectures in literature.

The most computationally demanding block in the digital front end of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Finite impulse response (FIR) filters are employed as channel filters in SDR receivers. These channel filters must be less complex and reconfigurable. A new reconfigurable architecture for the implementation of channel filters based on frequency response masking (FRM) technique is proposed in this paper. Our architecture offers multiple levels of reconfigurability in addition to the inherent low complexity features offered by the FRM technique. Design results show that our method offers an average adder reduction of 37% over binary subexpression elimination (BSE) technique and 57% over canonical signed digit (CSD) based techniques.

The complexity of linear phase finite impulse response (FIR) filters used in the channelizer of a software defined radio (SDR) receiver is dominated by the complexity of coefficient multipliers. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) coefficients produce low complexity FIR filter coefficient multipliers. A new CSE algorithm based on the binary representation of filter coefficients is presented in the paper. Design examples of channel filters employed in the digital advanced mobile phone systems (D-AMPS) and personal digital cellular (PDC) receivers show that the proposed method offers an average adder reduction of 23% over the conventional CSD-based CSE method

The most computationally demanding block of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Reconfigurability and low complexity are the two key requirements of the SDR channelizers. Two new reconfigurable architectures of low complexity finite impulse response (FIR) filters for channelizers are proposed in this paper. Our methods are based on the binary common subexpression elimination (BCSE) algorithm. The proposed architectures are capable of operating at a high speed clock frequency of 109.7 MHz based on Xilinx's Virtex II 2v2000ff896-6 FPGA for a 12-bit FIR filter coefficient. Design examples show that our method offers an average reduction of 23% in the number of addition operations compared to the conventional FIR filter implementations

The South Asian languages are well-known for their replicative words. In these languages, words of almost all the grammatical categories can occur in their reduplicative form. Hindi is one such language which is quite rich in having various types of replicative words in its lexicon. The traditional grammars and some of the research works have discussed the topic to some extent, particularly from the point of view of their descriptions and classifications. However, a detailed study of the topic becomes significant in view of the complexity involved in handling of such replicative words in the area of natural language processing, particularly for machine translation. In this paper, we discuss different types of replicative words in Hindi and their syntactic and semantic characteristics to formulate rules and strategies to identify their multiple functions and mapping patterns in English for machine translation from Hindi to English.