This paper presents an inductor-first tri-path (IFTP) buck converter suitable for USB power delivery adapter to charge 1-2 cell battery. The proposed topology adopts the inductor-first strategy and the tri-path strategy of one inductor path and two capacitor paths to extend the output voltage conversion range, realize the continuous input current, eliminate the input EMI noise, and reduce the inductor current. In addition, a phase-interleaved symmetric inductor-first tri-path (PIS-IFTP) buck converter is proposed to alleviate the inrush current in the flying capacitor under extreme duty cycle of IFTP converter, while further reducing inductor current ripple. Two experimental prototypes for 9 V input to 3-8.4 V ouput have been developed, demonstrating excellent ability of IFTP and PIS-IFTP topologies to reduce inductor current and achieve continuous input current over the whole duty cycle and load range. The experimental results validate that the prototypes provide a wide voltage conversion range of 1/3-1 and a maximum output current of 1.8 A. The peak efficiency of IFTP is 93% at$V_{OUT} \,\, =6.6$V, while the peak efficiency of PIS-IFTP is 94.5% at$V_{OUT} \,\, =3.3$V.

This paper presents an efficient global hysteresis control for output voltage regulation in order to improve the overall system efficiency. Compared with the conventional regulating-rectifying schemes in receiver, the proposed method achieves high light-load end-to-end (E2E) efficiency by shutting down the transmitter (TX) during freewheeling operation period of the rectifier. In addition, a carrier-less pulse-resonant-current modulation technique is proposed to efficiently wake up TX in time. Besides, the residual power of the TX coil in shutdown phase is recycled to further enhance the efficiency. This proposed wireless power transfer system is designed in a 0.18µm BCD process, and regulates an output voltage of 3V. Simulation results show that the maximum output power is 450mW with a high light-load E2E efficiency of 55.9%. The efficiency improvement reached 27.6% compared with the RX regulation only. For a load switching between 15mA and 150mA, the transient response is less than 100ns.

In this paper, a fully integrated low-dropout regulator (LDO) using voltage-to-time conversion (VTC) technique is presented for under-1 V supply voltage application. A synchronous VTC technique is proposed using constant-current (CC) charging and discharging to achieve high loop gain. A high-gain charge pump (CP) is proposed to improve power-supply-rejection (PSR). Furthermore, an asynchronous step detection recovery technique is proposed to achieve fast transient response. A frequency-adaptive oscillator is proposed to remove the noise of the clock signal. The proposed LDO is designed in 28-nm process to achieve a droop voltage of 104 mV at load current transient of 90 mA. The proposed LDO achieves PSR of -77 dB at ILOAD=100 mA and PSR of -65 dB at ILOAD=10 mA for 1-kHz supply ripple frequency. The quiescent current is 32 µA and the peak current efficiency is 99.98%.

This paper proposes a loop-free self-balancing technique of flying capacitor for three-level buck converter. The pro-posed converter utilizes two balancing switches in self-balancing circuit, which can adaptively change the series and parallel structure of flying capacitors at different working phases. In two operating modes of duty cycle less than 0.5 and greater than 0.5, the converter can stabilize the flying capacitor voltages at$V_{IN}\mathbf{/2}$without any balancing feedback calibration loops. This three-level converter prototype is designed in$\mathbf{0.18\mu \mathrm{m}}$BCD process. When input voltage is set to 6V, the converter can provide a 0.4-5.6V wide output voltage range and automatically calibrate flying capacitor voltage to 3V under different conversion ratios and load currents. Simulation results show that the maximum output voltage ripple and inductor current ripple are 2.5mV and 174mA respectively when conversion ratio is equal to 0.25 or 0.75.

This paper presents a novel single-stage dual-output wireless power transfer system with an adaptive global power control. The power of freewheeling mode mentioned in the traditional reconfigurable regulating rectifier is used as another output, which achieves high light-load power conversion efficiency (PCE) of the receiver. The voltage of one channel is regulated by a local constant on-time control, while another channel is regulated by the adaptive global power control. In this way, all of the received power is almost transmitted to the output. This proposed wireless power transfer system is designed in a 0.18 μrn BCD process, and regulates two outputs voltage of 4 V each. The maximum output power is 840 m W with a peak PCE of 93.1%. Compared with the local voltage-regulation, the light-load efficiency improvement reached 17.5%.

This paper presents a novel constant on-time (COT) single-stage reconfigurable regulating rectifier for wireless power transfer system. Compared with the discrete multi-cycle pulsewidth modulation technique adopting in the prior-art regulating rectifiers, the proposed rectifier achieves high regulating resolution by adjusting the duty ratio continuously and smoothly. In addition, the load-transient response is much faster with the COT control method. In order to optimize the output voltage ripples, the regulating cycle is designed to be small via minimizing the on-time. This single-stage wireless power receiver is designed in a 0.18$\mu$m BCD process, and regulates an output voltage of 5V. Simulation results show that the maximum output power is 850mW with a peak efficiency of 93.2% and a minimum regulating cycle of 0.12$\mu$s. For a load switching between 50mA and 170mA, the response of the proposed rectifier is instant with the unnoticeable overshoot and undershoot.

This paper presents a current-injection-based balancing circuit for three-level DC-DC converter. Compared with the method of adjusting duty cycle to achieve flying capacitor balance, the proposed circuit avoids the unbalanced problem without affecting the frequency. In order to adjust the flying capacitor voltage adaptively, a digital controlled feedback loop with 9-bit counter is adopted. The three-level DC-DC converter is designed in a 0.18μ m BCD process, and the input voltage range is 3-6V. Simulation results show that the proposed converter has a good performance of flying capacitor balance with a peak efficiency of 96.8%. The output voltage ripple and inductor current ripple can reach 0.15% and 1.06% of the output voltage and load current, respectively.

This paper presents a high-voltage inverting converter implemented by reconfiguring a buck DC-DC regulator. The negative output voltage is generated from a positive input voltage by exchanging the output and ground on a buck converter. In this way, the complexity of circuit design is greatly reduced. The converter adopts constant on-time control with on-chip ripple compensation and output DC offset elimination techniques to achieve fast transient response and highly accurate output voltage, which also allows the use of output capacitor with low equivalent series resistance (RESR). In addition, an internal bootstrap circuit for high-side driver is proposed in place of conventional LDO structure to improve the efficiency. The converter is fabricated in 0.18-$\mu$m BCD process. The input voltage is in the range from 5V to 48V. The measurement results show that the transient response is about 220$\mu$s and the overshoot or undershoot voltage is less than 190mV when the load transient between 100mA and 500mA for switching frequency of 300kHz, input voltage of 24V and output voltage of-12V.

A fully-integrated relaxation oscillator with a typical frequency of 1.37 MHz is proposed. Neither comparators nor the reference voltage is required in the proposed oscillator. A constant with temperature (CWT) current source has been utilized to achieve good temperature stability. Moreover, a conventional comparator has been replaced with a voltage controlled delay element (VCDE) to avoid the comparator offset effect. Furthermore, frequency variation against supply voltage has been eliminated by matching bias voltages of the current starved delay element (CSDE) in the ramp generator and VCDE. The proposed relaxation oscillator is implemented with 0.25 μm BCD process. The measured results show that the frequency variation against supply voltage is within ±0.6%.

This paper proposes a soft-start method with the features of a small on-chip capacitor and start stability for dc–dc converters. During the soft-start process, a slowly and linearly ramped-up voltage reference is generated based on the principle of the small on-chip capacitor charged by an oscillator-controlled pulse current to replace the normal reference. Meanwhile, the switching frequency is also reduced so that the inductor current has more time to decay and massive inrush current can be avoided. However, in this way, the system may be unstable in that the bandwidth could not keep less than 1/7 of the reduced switching frequency. In this paper, an error amplifier (EA) with gain-degeneration is proposed to solve this problem. When the switching frequency is reduced, the gain of the EA is also reduced and the bandwidth becomes narrower accordingly. A dc–dc converter using the proposed soft-start method has been implemented with a 0.5-$\mu{\rm m}$CMOS process. Experimental results show that a soft-start period of 600$\mu{\rm s}$is achieved with an on-chip capacitor of 15 pF. Furthermore, both the output voltage and inductor current rise smoothly without oscillation and overshoot during the startup process.