Generative adversarial networks (GANs) are promising for a range of applications, including image translation and denoising, as well as synthetic data generation. These applications can be mapped to memristive crossbar arrays (MCAs) for ultra-high energy efficiency and portability. However, conductance variation within analog crossbars degrades the quality of the GAN outputs and necessitates robust post-manufacturing testing. We propose a two-stage adaptive test framework for compute-in-memory (CiM) based GANs, comprising an exhaustive test and a compact test. The exhaustive test measures the inception score of a device under test (DUT) by applying a large number of noise vectors, called the exhaustive noise set. To reduce test time, a compact test estimates the inception score of a DUT from a carefully chosen subset of these vectors, called the compact noise set. The compact noise set is determined by a binary mask optimized with a novel backpropagation-guided algorithm to minimize the difference between the estimated and true inception scores of the DUTs. Finally, to leverage both the accuracy of the exhaustive test and the speed of the compact test, the proposed adaptive test framework first applies the compact test to every DUT. Only the DUTs that yield low confidence in classifications are then subjected to the exhaustive test. Experiments show that this adaptive approach achieves less than 1% test escapes while offering up to 7.26× speedup compared to exhaustive test.

Transformer networks have achieved remarkable success in Natural Language Processing (NLP) and Computer Vision applications. However, the underlying large volumes of Transformer computations demand high reliability and resilience to soft errors in processor hardware. The objective of this research is to develop efficient techniques for design of error resilient Transformer architectures. To enable this, we first perform a soft error vulnerability analysis of every fully connected layers in Transformer computations. Based on this study, error detection and suppression modules are selectively introduced into datapaths to restore Transformer performance under anticipated error rate conditions. Memory access errors and neuron output errors are detected using checksums of linear Transformer computations. Correction consists of determining output neurons with out-of-range values and suppressing the same to zero. For a Transformer with nominal BLEU score of 52.7, such vulnerability guided selective error suppression can recover language translation performance from a BLEU score of 0 to 50.774 with as much as 0.001 probability of activation error, incurring negligible memory and computation overheads.

While resistive random access memory (RRAM) based deep neural networks (DNN) are important for low-power inference in IoT and edge applications, they are vulnerable to the effects of manufacturing process variations that degrade their performance (classification accuracy). However, to test the same post-manufacture, the (image) dataset used to train the associated machine learning applications may not be available to the RRAM crossbar manufacturer for privacy reasons. As such, the performance of DNNs needs to be assessed with carefully crafted dataset-agnostic synthetic test images that expose anomalies in the crossbar manufacturing process to the maximum extent possible. In this work, we propose a dataset-agnostic post-manufacture testing framework for RRAM-based DNNs using Entropy Guided Image Synthesis (EGIS). We first create a synthetic image dataset such that the DNN outputs corresponding to the synthetic images minimize an entropy-based loss metric. Next, a small subset (consisting of 10–20 images) of the synthetic image dataset, called the compact image dataset, is created to expedite testing. The response of the device under test (DUT) to the compact image dataset is passed to a machine learning based outlier detector for pass/fail labeling of the DUT. It is seen that the test accuracy using such synthetic test images is very close to that of contemporary test methods.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Compute-in-memory (CiM) based convolutional neural network (CNN) accelerators achieve low-power inference, utilizing memristive crossbar arrays for matrix multiplications. However, inherent conductance variations within the crossbar introduce computational errors. These errors propagate to the CNN output and cause image misclassification, leading to substantial accuracy degradation. This paper addresses the critical challenge of efficient and reliable post-manufacture testing for CiM-based CNN accelerators. We propose a novel test image sampling methodology, which iteratively applies sampled images from the CNN's testing dataset using progressive random sampling (PRS) to a device under test (DUT) and estimates a confidence interval for the DUT accuracy. Based on the confidence interval and the acceptable accuracy threshold, the test labels a DUT as “pass” or “fail”. Furthermore, if we have access to an initial set of DUTs, we apply the images from the CNN's testing dataset to these DUTs and leverage the DUT outputs to rank-order test images. We develop a sequential estimation test (SET) framework, where the images from the CNN's testing dataset are sequentially applied according to a predetermined rank and the test terminates when a DUT can be confidently labeled as “pass” or “fail” based on the applied images. In each case, the number of applied test images adapts to the quality of the DUT. Experiments show that PRS and SET achieve$2.2\times$and$4.6\times$speedup compared to state-of-the-art test methodologies.

Stringent quality requirements for safety-critical applications drive the demand for "zero defects" in modern ICs. In this context, delay characterization of standard cells for resistive open defects is an increasing concern due to aggressive timing margins in digital circuits. The problem is made worse by the large number of open defect sites in standard cells, combined with a wide range of defect resistance values for each site. This incurs possible prohibitive costs for defect simulation and characterization. To alleviate this complexity, we propose Resistive Fault Dominance (RFD) for resistive open defects. RFD eliminates simulations of certain open defects with intermediate defect resistance values that are guaranteed to exceed specified timing margins for standard cells, based on tests for specific "dominant" open defects. This can significantly reduce the computational costs of cell library characterization and simulation effort by 84%-91%. An algorithmic fault simulation methodology for resistive open defects on parasitic-extracted (PEX) transistor-level netlist is developed.

Online deep reinforcement learning (deep RL)-based systems are being increasingly deployed in a variety of safety-critical applications. Due to the dynamic nature of the environments they work in, onboard reinforcement learning (RL) hardware is vulnerable to soft errors from radiation, thermal effects and electrical noise that corrupts the results of computations. Existing approaches to on-line error resilience in machine learning systems have relied on the availability of large training datasets to configure resilience parameters. This is not always feasible for online RL systems. Similarly, other approaches involving specialized hardware or modifications to training algorithms are difficult to implement for onboard RL applications. In contrast, we present a novel error resilience approach for online RL that leverages running statistics of neuron output values collected across the (real-time) RL training process to configure error detection thresholds (called checks) for the deep RL forward pass. Similarly, we formulate checks on the deep RL backward pass using running statistical thresholds on reduced-dimension checksums of online learning weight updates to rapidly detect and correct errors in online deep RL training. In this methodology, statistical concentration bounds leveraging running statistics are used to diagnose neuron outputs or weights as erroneous. The use of running statistics allows the checks to adapt to changes caused by continual on-line RL training. Erroneous neurons are set to zero (suppressed) in the forward pass. Erroneous weight updates are frozen, allowing nonerroneous weight updates to proceed and allowing online learning without rerunning training episodes. Our approach is compared against the state of the art and validated on several RL algorithms as well as a hardware validation platform.

Modern analog mixed-signal (AMS) devices manufactured in advanced CMOS processes pose significant testing and post-manufacture tuning challenges. Measurement of the specifications of AMS components is generally difficult as this requires the use of a range of dedicated tests while defect-based testing on the other hand, requires extensive defect simulations that are compute-intensive. To overcome these limitations, this research proposes OATT; a testing and post-manufacture tuning approach for AMS circuits that is designed to stress the performance of the device under test (DUT), formalize a statistical (multidimensional Gaussian) distribution of the expected response of known “good” devices (inliers), and use test limits grounded in theoretical statistics to classify all out-of-distribution devices (outliers) as “bad.” It is an alternative test approach in that it does not explicitly target simulation of defect mechanisms. Tuning is performed to transform individual outlier DUT responses to those resembling inlier devices by modulating hardware tuning knobs, such as bias voltages and currents, using a reinforcement learning algorithm. Circuit simulations and hardware results demonstrate the viability and efficiency of the proposed approach.

Modern wireless communications systems deploy massive MIMO systems with large numbers of transmit and receive antennas and analog–digital RF transceiver architectures that admit RF beamforming. These systems need to be tested and tuned postmanufacture to ensure signal quality. In analog architectures, this poses a problem due to the lack of observability of internal circuit nodes and due to the convergence of multiple RF beamforming chains into a combined baseband signal from which it is difficult to de-embed individual RF chain behaviors. Existing test techniques estimate nonlinearities in RF chains up to the third order and require significant frequency bandwidth to test multiple RF chains in a MIMO system in parallel, thereby reducing the overall test time. In this research, to improve testing efficiency, overlapping test tones over a minimal frequency range are applied to each of the MIMO RF chains in parallel, allowing specifications of individual RF chains up to fifth-order distortion to be determined accurately. For postmanufacture tuning, a response feature clustering approach followed by an implicit cost-driven tuning procedure is proposed. Tuning for error vector magnitude (EVM) and signal-to-interference ratio (SiNR) is performed under power constraints. Experimental results show that the proposed parallel testing methodology is 1.7$\times$more frequency-efficient than existing techniques, and the proposed postmanufacture tuning algorithm can tune a receiver with four RF chains in 1.8 ms.

Resistive random access Memory (RRAM) based spiking neural networks (SNN) are becoming increasingly attractive for pervasive energy-efficient classification tasks. However, such networks suffer from degradation of performance (as determined by classification accuracy) due to the effects of process variations on fabricated RRAM devices resulting in loss of manufacturing yield. To address such yield loss, a two-step approach is developed. First, an alternative test framework is used to predict the performance of fabricated RRAM based SNNs using the SNN response to a small subset of images from the test image dataset, called the SNN response signature (to minimize test cost). This diagnoses those SNNs that need to be performance-tuned for yield recovery. Next, SNN tuning is performed by modulating the spiking thresholds of the SNN neurons on a layer-by-layer basis using a trained regressor that maps the SNN response signature to the optimal spiking threshold values during tuning. The optimal spiking threshold values are determined by an off-line optimization algorithm. Experiments show that the proposed framework can reduce the number of out-of-spec SNN devices by up to 54% and improve yield by as much as 8.6%.

Variability-induced accuracy degradation of RRAM-based DNNs is of great concern due to their significant potential for use in future energy-efficient machine learning architectures. To address this, we propose a two-step process. First, an enhanced testing procedure is used to predict DNN accuracy from a set of compact test stimuli (images). This test response (signature) is simply the concatenated vectors of output neurons of intermediate and final DNN layers over the compact test images applied. DNNs with a predicted accuracy below a threshold are then tuned based on this signature vector. Using a clustering based approach, the signature is mapped to the optimal tuning parameter values of the DNN (determined using off-line training of the DNN via back-propagation) in a single step, eliminating any post-manufacture training of the DNN weights (expensive). The tuning parameters themselves consist of the gains and offsets of the ReLU activation of neurons of the DNN on a per-layer basis and can be tuned digitally. Tuning is achieved in less than a second of tuning time, with yield improvements of over 45% with a modest accuracy reduction of 4% compared to digital DNNs.

Prevalent test strategies for analog/mixed-signal systems rely on either (a) prediction of device-under-test (DUT) design specifications from observed test responses to carefully crafted alternate test stimulus, or (b) detecting outliers from known optimized test response statistics of devices subjected to expected manufacturing process variations. In both of these test paradigms, misclassification of DUTs (false positives and false negatives) is not explicitly considered during test generation itself due to computational complexity, but rather based on post-test determination of test acceptance thresholds. In this paper, we propose a novel test generation approach based on hyperdimensional clustering, that explicitly targets DUT misclassification rate during test stimulus generation itself. The use of hyperdimensional vectors for clustering good and bad devices along with a set of simple vector operations for training and inference allows fast determination of misclassification rate within the test generation procedure itself. Experimental results show that the test generation times are reduced by 15X with significant improvements in DUT misclassification rate.

Time-to-first-spike (TTFS) encoded spiking neural networks (SNNs), implemented using memristive crossbar arrays (MCA), achieve higher inference speed and energy efficiency compared to artificial neural networks (ANNs) and rate encoded SNNs. However, memristive crossbar arrays are vulnerable to conductance variations in the embedded memristor cells. These degrade the performance of TTFS encoded SNNs, namely their classification accuracy, with adverse impact on the yield of manufactured chips. To combat this yield loss, we propose a post-manufacture testing and tuning framework for these SNNs. In the testing phase, a timing encoded signature of the SNN, which is statistically correlated to the SNN performace, is extracted. In the tuning phase, this signature is mapped to optimal values of the tuning knobs (gain parameters), one parameter per layer, using a trained regressor, allowing very fast tuning (about 150ms). To further reduce the tuning overhead, we rank order hidden layer neurons based on their criticality and show that adding gain programmability only to 50% of the neurons is sufficient for performance recovery. Experiments show that the proposed framework can improve yield by up to 34% and average accuracy of memristive SNNs by up to 9%.

Resistive random access memory (RRAM) based memristive crossbar arrays enable low power and low latency inference for convolutional neural networks (CNNs), making them suitable for deployment in IoT and edge devices. However RRAM cells within a crossbar suffer from conductance variations, making RRAM-based CNNs vulnerable to degradation of their classification accuracy. To address this, the classification accuracy of RRAM based CNN chips can be estimated using predictive tests, where a trained regressor predicts the accuracy of a CNN chip from the CNN’s response to a compact test dataset. In this research, we present a framework for co-optimizing the pixels of the compact test dataset and the regressor. The novelty of the proposed approach lies in the ability to co-optimize individual image pixels, overcoming barriers posed by the computational complexity of optimizing the large numbers of pixels in an image using state-of-the-art techniques. The co-optimization problem is solved using a three step process: a greedy image down selection followed by backpropagation driven image optimization and regressor fine-tuning. Experiments show that the proposed test approach reduces the CNN classification accuracy prediction error by $31 \%$ compared to the state of the art. It is seen that a compact test dataset with only 2-4 images is needed for testing, making the scheme suitable for built-in test applications.

Process variability effects and subtle defect mechanisms in deeply scaled analog/mixed-signal/RF (AMS) silicon technologies combine in malicious ways to increase DPPMs of mixed-signal Systems-on-Chips (SoCs). This has driven the need to increase defect coverage while minimizing testing costs. However, testing embedded AMS components in mixed-signal SoCs has always been a challenge due to test access limitations and requirement for labeled data. In this work, we focus on eliminating the requirement for labeled data. As such, rather than measuring the specification values of embedded AMS components, it is more expedient to devise tests using on- chip resources along with low cost mechanisms for identifying outlier behaviors in measured data to identify devices with parametric and catastrophic defects. To resolve this, what is needed are : (a) a test generation methodology that separates outlier from inlier device behaviors making them easily detectable and (b) a response analysis approach that can draw boundaries between multi-dimensional "good" and "outlier" behaviors with such computational ease that it can be invoked in each test generation iteration to quantify the quality of the test being considered. In this context, a novel test stimulus generation approach using clustering of test data in hyperdimensional spaces is developed that maximizes the similarities of inlier devices in the hyperdimensional space thereby allowing outlier devices to be identified easily by their corresponding hypervector representations from their dissimilarity with hypervectors of inlier devices. Such an approach overcomes the major drawback of prior approaches by eliminating the requirement for labeled data. For decision-making, a one-class hyperdimensional classifier that relies on a single cluster boundary (as opposed to complex boundaries in nonlinear spaces), is used to separate "good" vs. "bad" devices. The classifier is computationally efficient, outperforms existing techniques for defect coverage, and drives the search for the optimal test stimulus. Simulation results on test circuits prove the benefits of the proposed approach over prior testing methods.

Emerging brain-inspired hyperdimensional computing (HDC) algorithms are vulnerable to timing and soft errors in associative memory used to store high-dimensional data representations. Such errors can significantly degrade HDC performance. A key challenge is error correction after an error in computation is detected. This work presents two novel error resilience frameworks for hyperdimensional computing systems. The first, called the checksum hypervector encoding (CHE) framework, relies on creation of a single additional hypervector that is a checksum of all the class hypervectors of the HDC system. For error resilience, elementwise validation of the checksum property is performed and those elements across all class vectors for which the property fails are removed from consideration. For an HDC system with K class hypervectors of dimension D, the second cross-hypervector clustering (CHC) framework clusters $D , K$- dimensional vectors consisting of the i-th element of each of the K HDC class hypervectors, $1 \le \quad i \quad \le \quad K$. Statistical properties of these vector clusters are checked prior to each hypervector query and all the elements of all K-dimensional vectors corresponding to statistical outlier vectors are removed as before. The choice of which framework to use is dictated by the complexity of the dataset to classify. Up to three orders of magnitude better resilience to errors than the state-of-the-art across multiple HDC high-dimensional encoding (representation) systems is demonstrated.11Our codes and data are available at https://github.com/mmejri3/er-hdc

Modern deep neural networks (DNNs) are deployed across a wide range of applications, from medical robotics to autonomous driving, where safety and reliability are key concerns. The complexity, speed, and low-power operation of the underlying hardware makes them vulnerable to soft errors that corrupt the results of computations and memory accesses. Existing approaches to error resilience are either expensive in terms of overhead, require DNN retraining or applicable to only specific hardware domains. In contrast, we present a novel error resilience approach that does not require DNN retraining and scales across computation as well as weight parameter errors. In the proposed methodology, the statistics of gradients of neuron output values relative to adjacent neurons in an ordering of neurons allow tight theoretically grounded thresholding of neuron outputs to diagnose erroneous neuron outputs. These are then set to zero (suppressed) for error resilience. A low-overhead error diagnosis module is used for this purpose and is designed using gradient statistics collected across the training dataset of the DNN. Our approach is compared against state of the art error resilience techniques and validated on multiple datasets, networks and error scenarios as well a hardware test case.

Spiking Neural Networks (SNNs) can be implemented with power-efficient digital as well as analog circuitry. However, in Resistive RAM (RRAM) based SNN accelerators, synapse weights programmed into the crossbar can differ from their ideal values due to defects and programming errors, degrading inference accuracy. In addition, circuit nonidealities within analog spiking neurons that alter the neuron spiking rate (modeled by variations in neuron firing threshold) can degrade SNN inference accuracy when the value of inference time steps (ITSteps) of SNN is set to a critical minimum that maximizes network throughput. We first develop a recursive linearized check to detect synapse weight errors with high sensitivity. This triggers a correction methodology which sets out-of-range synapse values to zero. For correcting the effects of firing threshold variations, we develop a test methodology that calibrates the extent of such variations. This is then used to proportionally increase inference time steps during inference for chips with higher variation. Experiments on a variety of SNNs prove the viability of the proposed resilience methods.

Online reinforcement learning (RL) based systems are being increasingly deployed in a variety of safety-critical applications ranging from drone control to medical robotics. These systems typically use RL onboard rather than relying on remote operation from high-performance datacenters. Due to the dynamic nature of the environments they work in, onboard RL hardware is vulnerable to soft errors from radiation, thermal effects and electrical noise that corrupt the results of computations. Existing approaches to on-line error resilience in machine learning systems have relied on availability of the large training datasets to configure resilience parameters, which is not necessarily feasible for online RL systems. Similarly, other approaches involving specialized hardware or modifications to training algorithms are difficult to implement for onboard RL applications. In contrast, we present a novel error resilience approach for online RL that makes use of running statistics collected across the (real-time) RL training process to configure error detection thresholds without the need to access a reference training dataset. In this methodology, statistical concentration bounds leveraging running statistics are used to diagnose neuron outputs as erroneous. These erroneous neurons are then set to zero (suppressed). Our approach is compared against the state of the art and validated on several RL algorithms involving the use of multiple concentration bounds on CPU as well as GPU hardware.

Prevalent specification-based AMS testing techniques require the use of complex test circuits or regressors that are difficult to implement on-chip as well as suffer from coverage loss when devices are under-specified. Complementary defect based testing techniques require the simulation of explosively large defect sets under assumed failure mechanisms. We overcome these limitations in our proposed approach OATT; an Outlier-oriented Alternative Testing and Tuning methodology. OATT maximizes the number and magnitude of the statistical principal components (PCA) of the time-domain DUT test response vectors across diverse manufacturing process corners. This allows construction of a multi-dimensional Gaussian probability density model that characterizes the distribution of DUT responses in the principal components domain. Outliers of this probability density model are classified as defective devices using calibrated confidence ellipses, implicitly detecting devices with parametric as well as hard defects. The embedded DUT response is acquired using coherent undersampling and does not require explicit signal reconstruction. Post-manufacture tuning is performed by minimizing the statistical distance of the DUT response in the PCA domain from the nominal Gaussian model using multi-arm bandit reinforcement learning. Simulation results demonstrate the viability and promise of the proposed approach.

Emerging wireless technologies employ MIMO beamforming antenna arrays to improve channel Signal-to-Noise Ratio (SNR). The increased dynamic range of channel SNR values that can be accommodated, creates power stress on Radio Frequency (RF) electronic circuitry. To alleviate this, we propose an approach in which the circuitry along with other transmission coding parameters can be dynamically tuned in response to channel SNR and beam-steering angle to either minimize power consumption or maximize throughput in the presence of manufacturing process variations while meeting a specified Bit Error Rate (BER) limit. The adaptation control policy is learned online and is facilitated by information obtained from testing of the RF circuitry before deployment.

Deep learning techniques have been widely adopted in daily life with applications ranging from face recognition to recommender systems. The substantial overhead of conventional error tolerance techniques precludes their widespread use, while approaches involving median filtering and invariant generation rely on alterations to DNN training that may be difficult to achieve for larger networks on larger datasets. To address this issue, this paper presents a novel approach taking advantage of the statistics of neuron output gradients to identify and suppress erroneous neuron values. By using the statistics of neurons’ gradients with respect to their neighbors, tighter statistical thresholds are obtained compared to the use of neuron output values alone. This approach is modular and is combined with accurate, low-overhead error detection methods to ensure it is used only when needed, further reducing its cost. Deep learning models can be trained using standard methods and our error correction module is fit to a trained DNN, achieving comparable or superior performance compared to baseline error correction methods while incurring comparable hardware overhead without needing to modify DNN training or utilize specialized hardware architectures.

In analog and mixed-signal (AMS) design, it is necessary to validate equivalence between the behavioral or netlist level description of an AMS system and its physical realization (device-under test, DUT) in silicon. If a discrepancy is found, relevant bugs need to be diagnosed to individual circuit modules for closer inspection. Typically, design bugs may exist in one or more circuit modules. In addition, parametric defects in silicon can also cause performance degradation. So a combination of such design “anomalies” needs to be debugged and triaged during silicon respin. A major difficulty is that neither the number of buggy modules, nor the nature of buggy module behaviors is known apriori. To diagnose and localize such bugs, we perform a set of bug emulation experiments (BEEs). In each experiment, one or more learning kernels are placed across modules in the high-level AMS model of the circuit and trained to replicate the buggy circuit output response to specialized test stimulus (this is a key innovation: concurrent bug learning). The test stimulus is optimized to expose behavioral differences between the expected and observed DUT response over the entire input space of the DUT. An error response clustering algorithm along with knowledge of the placement of the kernels is then used to guide successive BEEs for bug diagnosis. The algorithm converges when the minimum residual error across the ensemble of BEEs conducted cannot be further reduced through additional BEEs. The modules with inserted kernels for that BEE are the most likely buggy modules. Results on multiple mixed-signal designs prove the viability of the proposed approach.

Analog crossbar arrays have recently attracted significant attention due to their usefulness for deep neural net (DNN) computations with ultra-low power consumption. However, recent studies have shown that DNNs implemented with such crossbar arrays suffer from as high as 30% degradation in performance due to the effects of manufacturing process variability effects resulting in degradation of their functional safety. One way to test these DNNs is to apply an exhaustive set of test images to each device to ascertain its performance. This is expensive and time-consuming. We propose an alternative test scheme in which a small subset of test images is applied to each DNN and the classification accuracy of the DNN is predicted directly from observation of the final layer outputs of the network. This saves test cost while allowing binning of DNNs for performance. Experimental results for a variety of test cases are presented and show test efficiency improvements of 10.3X over testing with the exhaustive test image set.

In top-down analog and mixed-signal design, a key problem is to ensure that the netlist or physical design does not contain unanticipated behaviors. Mismatches between netlist level circuit descriptions and high level behavioral models need to be captured at all stages of the design process for accuracy of system level simulation as well as fast convergence of the design. To support the above, we present a guided test generation algorithm that explores the input stimulus space and generates new stimuli which are likely to excite differences between the model and its netlist description. Subsequently, a recurrent neural network (RNN) based learning model is used to learn divergent model and netlist behaviors and absorb them into the model to minimize these differences. The process is repeated iteratively and in each iteration, a Bayesian optimization algorithm is used to find optimal RNN hyperparameters to maximize behavior learning. The result is a circuit-accurate behavioral model that is also much faster to simulate than a circuit simulator. In addition, another sub-goal is to perform design bug diagnosis to track the source of observed behavioral anomalies down to individual modules or small levels of circuit detail. An optimization-based diagnosis approach using Volterra learning kernels that is easily integrated into circuit simulators is proposed. Results on representative circuits are presented.

For a dynamical system, safety is typically guaranteed by constraining the system states within a set defined a priori. A popular approach is to use control barrier functions (CBFs) that encode safety using a smooth function. However, typical constructions of the smooth function do not account for any notion of safety uncertainty for the system inside the safe set. Although, one can formulate uncertainty in the dynamics of the model in a CBF framework, observability of unmodeled dynamics is difficult, particularly in an online setting. Addressing these drawbacks, we present a novel formulation for synthesizing the CBF smooth function by taking into account safety uncertainty using online measurements of the system states. This uncertainty is encoded by computing the posterior variance using Gaussian processes conditioned on past measurement states. Our approach only requires observability of system states rather than the system dynamics. By incorporating safety uncertainty, the safe set can be dynamically expanded or compressed. This is achieved by computing a local safety map online at the present location and identifying samples with minimal safety exceeding the current safety limit. As more data is collected, the safety margin increases. Hence, these minimally safe exploratory samples can be used to expand the current safe set incrementally. We validate our approach experimentally by expanding an initial safe set, along x and y positions independently, for a quadrotor with safety. The experiment video can be seen at: https://youtu.be/9qvOf1UpRPw.

The reliability of Deep Neural Networks (DNNs) is of great concern due to their widespread use in safety-critical applications. Prior research has focused on adaptation of algorithm based fault tolerance schemes for error detection in the dot product (linear) computations of DNNs. In this research, we show that compact machine-learned algorithmic checks inspired by prior work on linear checksums but adapted to the overall nonlinear nature of DNN computations can be used to detect both soft errors and image-triggered trojans in real-time. Experiments indicate that the method incurs low computation overhead (4%-20%), while achieving high coverage (up to 90% for soft errors and 99% for image-triggered attacks).

State information transmitted across communication links of distributed power grids can be compromised by security attacks on these links causing power fluctuations and outage. Encryption of transmitted data is a first line of defense against such attacks but the entire network can be compromised if the keys are broken such as through side-channel attacks on encryption hardware. We propose the use of low cost state checksums as a critical second line of defense against such attacks. It is seen that stealth and replay attacks that can defeat prior residual filter based attack detection methods, can be detected using state checksums. Further, the proposed attack detection approach is highly resilient to adversarial counterattacks. A key benefit is low latency diagnosis of compromised communication links (and thereby sub-networks) not possible through use of encryption techniques alone. Diagnosis is driven by a dynamic binary search driven partitioning of system states into compromised vs. nominal subsets. We demonstrate through simulation of IEEE benchmark systems and two high-voltage power grids that our proposed scheme significantly reduces the latency of attack mitigation with lower complexity in comparison to prior research.

Autonomous systems that rely on multiple interacting subsystems require a high degree of reliability and resilience to a wide range of failures in those subsystems. In this work the effects of electro-mechanical failures in the steer-by-wire, brake-by-wire and vehicle controller subsystems of autonomous vehicles on subsystem and vehicle level performance are studied. A machine learning assisted correction approach using Gaussian Processes to learn fault dynamics on-line is developed and its efficacy is demonstrated under a variety of vehicle maneuvers and failure conditions at the subsystem and vehicle levels.

Achieving high yield in deep-submicron technologies is challenging due to the presence of unforeseen defect mechanisms, requiring increases in test complexity and efficiency. We focus on shorts within standard cells which are traditionally targeted by DC tests. Recent research has shown the need for multi-pattern tests where intermediate defect resistance values are concerned, as opposed to extreme values considered by prevalent test techniques. In this research, we show that there exist ranges of short defect resistance values that escape traditional DC tests while incurring unexpectedly large delay values for specific two-pattern stimuli. It is seen that these resistance values are approximately in the range of defect resistance values observed for realistic short defects in industry. These defects must therefore be prioritized from a circuit level critical path delay testing perspective to minimize overall circuit DPPM. Such catastrophic increase in delay is due to the fact that specific shorts in standard cells influence the delays of logic gates feeding into and out of the standard cell, resulting in path delay increase of 50X-SOX with respect to the delay of a single cell. Two-pattern tests are derived for such faults and simulation results on standard cell designs and ripple carry adders are presented to further our arguments.

Successful deployment of autonomous systems in a wide range of societal applications depends on error-free operation of the underlying signal processing and control functions. Real-time error detection in nonlinear systems has mostly relied on redundancy at the component or algorithmic level causing expensive area and power overheads. This paper describes a real-time error detection methodology for nonlinear control systems for detecting sensor and actuator degradations as well as malfunctions due to soft errors in the execution of the control algorithm on a digital processor. Our approach is based on creation of a redundant check state in such a way that its value can be computed from the current states of the system as well as from a history of prior observable state values and inputs (via machine learning algorithms). By checking for consistency between the two, errors are detected with low latency. The method is demonstrated on two test case simulations - an inverted pendulum balancing problem and a sliding mode controller driven brake-by-wire (BBW) system. In addition, hardware results from error injection experiments in an ARM core representation on an FPGA and artificial sensor degradations on a self-balancing robot prove the practical feasibility of implementation.

Spectrum-based Fault Localization (SFL) approaches aim to efficiently localize faulty components from examining program behavior. This is done by collecting the execution patterns of various combinations of components and the corresponding outcomes into a spectrum. Efficient fault localization depends heavily on the quality of the spectra. Previous approaches, including the current state-of-the-art Density- Diversity-Uniqueness (DDU) approach, attempt to generate “good” test-suites by improving certain structural properties of the spectra. In this work, we propose a different approach, Multiverse Analysis, that considers multiple hypothetical universes, each corresponding to a scenario where one of the components is assumed to be faulty, to generate a spectrum that attempts to reduce the expected worst-case wasted effort over all the universes. Our experiments show that the Multiverse Analysis not just improves the efficiency of fault localization but also achieves better coverage and generates smaller test-suites over DDU, the current state-of-the-art technique. On average, our approach reduces the developer effort over DDU by over 16% for more than 92% of the instances. Further, the improvements over DDU are indeed statistically significant on the paired Wilcoxon Signed-rank test.

In this paper we propose a framework for concurrent detection of soft computation errors in particle filters which are finding increasing use in robotics applications. The particle filter works by sampling the multi-variate probability distribution of the states of a system (samples called particles, each particle representing a vector of states) and projecting these into the future using appropriate nonlinear mappings. We propose the addition of a `check' state to the system as a linear combination of the system states for error detection. The check state produces an error signal corresponding to each particle, whose statistics are tracked across a sliding time window. Shifts in the error statistics across all particles are used to detect soft computation errors as well as anomalous sensor measurements. Simulation studies indicate that errors in particle filter computations can be detected with high coverage and low latency.

A key challenge with controlling complex dynamical systems is to accurately model them. However, this requirement is very hard to satisfy in practice. Data-driven approaches such as Gaussian processes (GPs) have proved quite effective by employing regression based methods to capture the unmodeled dynamical effects. However, GPs scale cubically with number of data points n, and it is often a challenge to perform realtime regression. In this paper, we propose a semi-parametric framework exploiting sparsity for learning-based control. We combine the parametric model of the system with multiple sparse GP models to capture any unmodeled dynamics. MultiSparse Gaussian Process (MSGP) uses multiple sparse models with unique hyperparameters for each one, thereby, preserving the richness and uniqueness of each sparse model. For a query point, a weighted sparse posterior prediction is performed based on N neighboring sparse models. Hence, the prediction complexity is significantly reduced from O(n3) to O(Npu2), p and u are data points and pseudo-inputs respectively for each sparse model. We validate MSGP's learning performance for a quadrotor using a geometric controller in simulation. Comparison with GP, sparse GP, and local GP shows that MSGP has higher prediction accuracy than sparse and local GP, with significantly lower time complexity than all three. We also validate MSGP on a real quadrotor setup for unmodeled mass, inertia, and disturbances. The experiment video can be seen at: https://youtu.be/zUk1ISux6ao.

Modern 5G and projected 6G wireless systems deploy massive MIMO systems with antenna arrays and novel RF transceiver architectures that admit RF beamforming. Testing and tuning of the underlying transceiver arrays on a per-transceiver basis is expensive and can be expedited through the use of parallel testing and tuning techniques that stimulate the entire array transceiver system concurrently. State of the art parallel testing techniques require frequency separation between the tones applied to individual RF chains due to combining of RF signals before down-conversion in analog beamforming MIMO systems. Test schemes that allow some frequency overlap are limited to testing only third order distortion. In this paper, we first present a parallel testing scheme for testing large MIMO transceiver arrays that is amenable to higher order distortion (upto fifth order) in the RF chains considered. Second, we propose a tuning scheme for the entire MIMO array which implicitly tunes for EVM system specifications without explicit knowledge of the relationship between the system test response, the system tuning knobs and the corresponding EVM and SINR specification values. A cost metric is formulated that allows such a solution using reinforcement (multi-arm bandit) learning driven system tuning. Significant yield improvement using this approach is demonstrated by simulation experiments.

The advent of pervasive autonomous systems such as self-driving cars and drones has raised questions about their safety and trustworthiness. This is particularly relevant in the event of on-board subsystem errors or failures. In this research, we show how encoded Extended Kalman Filter can be used to detect anomalous behaviors of critical components of nonlinear autonomous systems: sensors, actuators, state estimation algorithms and control software. As opposed to prior work that is limited to linear systems or requires the use of cumbersome machine learned checks with fixed detection thresholds, the proposed approach necessitates the use of time-varying checks with dynamically adaptive thresholds. The method is lightweight in comparison to existing methods (does not rely on machine learning paradigms) and achieves high coverage as well as low detection latency of errors. A quadcopter and an automotive steer-by-wire system are used as test vehicles for the research and simulation and hardware results indicate the overhead, coverage and error detection latency benefits of the proposed approach.

Recent advances in process technology have resulted in novel defect mechanisms making the test generation process very challenging. In addition to complete opens and shorts that can be represented via extreme defect resistance magnitudes, partial resistive opens and shorts are also of concern in deeply scaled CMOS technologies. For open defects with intermediate defect magnitude values, it has been shown that multi-pattern tests are necessary for defect exposure. We extend this approach to short defects with intermediate defect magnitude values to obtain a suite of multi-pattern tests for standard cell instances that cover complete as well as partial intra-cell open and short defects. A hierarchical scan-compatible SAT-based test generation approach for full scan sequential circuits is then proposed that allows such multi-pattern tests to be applied to the circuit via the scan infrastructure. A key innovation is the combined use of shift and capture operations along with launch-on-capture and launch-on-shift scan based test application for increased defect coverage. Resulting defect coverage improvements over conventional two-pattern tests are demonstrated on ISCAS89 benchmark circuits.

Test stimulus generation algorithms for analog/RF circuits rely on iterative simulation of the circuits concerned and are extremely computation-intensive. Our objective is to speed up test stimulus generation while allowing tests to be optimized dynamically (adapted) across diverse process corners that a device under test (DUT) is experiencing during manufacturing without compromising test quality. To achieve this, we propose to dynamically recognize devices from unknown process corners during manufacturing test and create Booleanized models of these devices from measurements performed on hardware. The cumulative ensemble of Booleanized models across different devices is used to (re-) optimize tests depending on observed performance statistics. The use of Booleanized models for test generation allows orders of magnitude speed up in test computation time while allowing emulation of devices long after they have shipped to the customer. The method is demonstrated using the alternative test methodology developed in prior research and allows the tests concerned to adapt to process shifts in a dynamic manner during device manufacture. The simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.

The rapid rise of self-driving cars and drones has raised questions about the safety of autonomous robotics deployed in society. Prior work on robust and adaptive control make assumptions about the boundedness of errors or require the use of full scale system models running in the background for control reference. In this research, we show how state space checks can be used to diagnose and compensate for errors in sensors, actuators and control program execution in nonlinear systems for robotic applications. The primary focus is on lightweight methods for mitigation of transient errors in sensor data and control program execution and parametric deviations in sensor circuitry and actuator subsystems. A quadcopter is used as a test vehicle for the research and simulation results indicate that errors can be compensated with high efficiency and low computation overhead.

Future pervasive autonomous systems such as un-manned land and air vehicles will need to be extremely resilient to failures in sensors, actuators and on-board electronics for the purpose of overall vehicle safety. While detection of failures in sensors and actuators has been addressed in the past, direct application of prior error checking schemes to complex autonomous systems with multiple actuators is difficult. This is due to the large numbers of system state variables involved, the resulting degraded ability to perform accurate error detection and most importantly, loss of the ability to perform accurate error diagnosis. In this research, a hierarchical error checking scheme is presented that allows errors in centralized as well as distributed control of autonomous systems to be detected with high accuracy and low latency while allowing error diagnosis down to individual sensor-actuator subsystems. Checking mechanisms for subsystems as well as centralized control are synthesized so as to ensure coverage of all sensors and actuator errors. The viability of the proposed technique is demonstrated using a quadcopter flight control system. High error coverage and diagnosis down to critical sensor-actuator subsystems is demonstrated.

Ensuring high defect coverage for advanced CMOS technology nodes has been a major challenge for the IC test industry. Traditional test methods using fault models such as stuck-at and transition faults with a primitive gate-level abstraction of design netlists have been shown to be inadequate for detecting open-circuit and short-circuit defects within instances of standard cells used in those netlists. Recent advances in Cell-Aware Test (CAT) using single pattern and two pattern tests have demonstrated increased coverage of such defects in industrial IC designs. However, the simulation overhead of defect characterization for all the cells in a library practically limits the size of defects that are explored to large magnitudes. Furthermore, certain effects such as charge sharing within cells can necessitate tests that span more than two time frames to expose subtle defects. This work, through simulation, identifies defects of certain sizes that can go undetected by current methods. It then proposes an algorithmic approach towards cell characterization that can result in faster identification of cell input stimuli vis-a-vis a defect simulation based method.

High operating speeds and use of aggressive fabrication technologies necessitate validation of mixed-signal electronic systems at every stage of top-down design: behavioral to netlist to physical design to silicon. At each step, design validation establishes the equivalence of lower level design descriptions against their higher level specifications. Prior research has leveraged state reachability analysis, nonconvex optimization, or performance specifications in order to generate tests. In contrast, we reformulate the systems under validation as a Markov decision process and examine the use of reinforcement-learning to provide a globally convergent solution, a means of “storing” the valuable information created during stimulus generation, and low-cost iterated generation. The integration of the proposed design validation methodology with deep-Q learning software and the suite of Cadence simulation tools is presented, validation results for selected design bugs in representative designs are analyzed, and the quality and efficiency of the proposed design validation methodology is discussed.

The successful deployment of autonomous real-time systems is contingent on their ability to recover from performance degradation of sensors, actuators, and other electro-mechanical subsystems with low latency. In this article, we introduce ALERA, a novel framework for real-time control law adaptation in nonlinear control systems assisted by system state encodings that generate an error signal when the code properties are violated in the presence of failures. The fundamental contributions of this methodology are twofold—first, we show that the time-domain error signal contains perturbed system parameters’ diagnostic information that can be used for quick control law adaptation to failure conditions and second, this quick adaptation is performed via reinforcement learning algorithms that relearn the control law of the perturbed system from a starting condition dictated by the diagnostic information, thus achieving significantly faster recovery. The fast (up to 80X faster than traditional reinforcement learning paradigms) performance recovery enabled by ALERA is demonstrated on an inverted pendulum balancing problem, a brake-by-wire system, and a self-balancing robot.

Flexible hybrid electronics (FHE) systems are an emerging technology that can be used in various applications such as automotive systems, energy harvesting, wireless transmission, and wearable electronics. However, due to wear and tear from stretching and twisting of the flexible substrate, interconnect designed onto flexible substrates are subject to loss of performance and failure. Therefore it becomes imperative to design low cost test coupons for flexible substrate interconnect that can be used to detect and diagnose interconnect failure due to onset of mechanical stress. In this paper, a monobit built-in test and diagnosis system for flexible electronic interconnect is introduced and verified in simulation. Methods for in-situ monitoring, signal reconstruction, impedance change detection and diagnosis are introduced. The proposed monobit architecture and associated algorithms achieve efficient test and diagnostics without the use of complex electronics such as needed for time-domain reflectometry (TDR).

Device aging is an important concern in nanoscale designs. Due to aging the electrical behavior of transistors embedded in an integrated circuit deviates from original intended one. This leads to performance degradation in the underlying device, and the ultimate device failure. This effect is exacerbated in emerging technologies. To be able to tailor effective aging mitigation schemes and improve the reliability of devices realized in cutting edge technologies, there is a need to accurately study the effect of aging in high performance industrial applications. According, this paper targets a high performance SRAM memory realized in 14nm FinFET technology and depicts how aging degrades the individual components of this memory as well as the interaction between them. Aging mitigation is critical not only from device reliability point of view but also regarding device security perspectives. It is essential to assure the security of the sensitive tasks performed by the security-sensitive circuits and to guarantee the security of information stored within these devices in the presence of aging. Accordingly in this paper, we also focus on aging-related security concerns and present the cases in which aging need to considered to preserve security.

In this research, a low cost error detection and correction approach is developed for multilayer perceptron networks, where checker neurons are used to encode hidden layer functions using independent training experiments. Error detection and correction is predicated on validating consistency properties of the encoded checks and shows that high coverage of injected errors can be achieved with extremely low computational overhead.

The last decade has seen tremendous advances in the transformation of ubiquitous control, computing and communication platforms that are anytime, anywhere. These platforms allow humans to interact with machines through sensing, control and actuation functions in ways not imaginable a few decades ago. While robust control techniques aim to maintain autonomous system performance in the presence of bounded modeling errors, they are not designed to manage large multi- parameter variations and internal component failures that are inevitable during lengthy periods of field deployment. To address the trustworthiness of autonomous systems in the field, we propose a cross-layer error resilience approach in which errors are detected and corrected at appropriate levels of the design (hardware-through software) with the objective of minimizing the latency of error recovery while maintaining high failure coverage. At the control processor level, soft errors in the digital control processor are considered. At the system level, sensor and actuator failures are analyzed. These impairments define the health of the system. A methodology for adapting the control procedure of the autonomous system to compensate for degraded system health is proposed. It is shown how this methodology can be applied to simple linear and nonlinear control systems to maintain system performance in the presence of internal component failures. Experimental results demonstrate the feasibility of the proposed methodology.

The last decade has seen tremendous advances in the application of artificial neural networks to solving problems that mimic human intelligence. Many of these systems are implemented using traditional digital compute engines where errors can occur during memory accesses or during numerical computation. While such networks are inherently error resilient, specific errors can result in incorrect decisions. This work develops a low overhead error detection and correction approach for multilayer artificial neural networks, here the hidden layer functions are approximated using checker neurons. Experimental results show that a high coverage of injected errors can be achieved with extremely low computational overhead using consistency properties of the encoded checks. A key side benefit is that the checks can flag errors when the network is presented outlier data that do not correspond to data with which the network is trained to operate.

High levels of integration in SoCs and SoPs is making pre as well as post-silicon validation of mixed-signal systems increasingly difficult due to: (a) lack of automated pre and postsilicon design checking algorithms and (b) lack of controllability and observability of internal circuit nodes in post-silicon. While digital scan chains provide observability of internal digital circuit states, analog scan chains suffer from signal integrity, bandwidth and circuit loading issues. In this paper, we propose a novel technique based on built-in state consistency checking that allows both pre as well as post-silicon validation of mixed-signal/RF systems without the need to rely on manually generated checks. The method is supported by a design-for-validation (DfV) methodology which systematically inserts a minimum amount of circuitry into mixed-signal systems for design bug detection and diagnosis purposes. The core idea is to apply two spectrally diverse stimuli to the circuit under test (CUT) in such a way that they result in the same circuit state (observed voltage/current values at internal or external circuit nodes). By comparing the resulting state values, design bugs are detected efficiently without the need for manually generated checks. No assumption is made about the nature of the detected bugs; the stimulus applied is steered towards those that are the most likely to detect design bugs. Test cases for both pre and post-silicon design bug detection and diagnosis prove the viability of the proposed BISCC approach.

With the wide proliferation of autonomous sense-and-control real-time systems (such as robots and self-driven cars), a key research objective is rapid recovery from the effects of anomalies and impairments arising from performance degradation of sensors and actuators and electro-mechanical subsystems due to field wear and tear. This must be achieved with minimal impact on system performance while maintaining low implementation overhead and high coverage of multi-parameter failure mechanisms. In this work, we propose a reinforcement learning framework for on-line control law adaptation in autonomous nonlinear systems assisted by system state encodings. These encodings are exploited to generate time-varying error signals whose (transient) waveforms in relation to the input stimulus, contain root-cause diagnostic information. This establishes a statistical correlation between the transient waveforms and the parameters of the optimal nonlinear controller under arbitrary multi-parameter perturbations of sensor/actuator and subsystem performances. Consequently this correlation is tapped, using pre-deployment supervised learning algorithms, to predict near-optimal controller parameter values whenever sufficiently large parameter deviations are detected (due to non-zero error signals). From these near-optimal starting conditions, an actor-critic reinforcement learning controller for nonlinear systems quickly converges to the optimal control law for the parameter-perturbed system (up to 10× faster than for systems not assisted by the diagnostic information provided by the state encoding driven error signal above). We implement the proposed methodology on two nonlinear systems demonstrating fast performance recovery in real time.

The proliferation of cyber physical systems in society, from the smart grid to sensor networks and robots has raised the importance of error resilience in signal processing and control systems to unprecedented levels. Resilience to errors in sensing and control algorithm execution in processors all the way down to circuits for sensing and actuation is of critical importance in safety-critical applications where undetected errors can have disastrous consequences. In this presentation, we describe how ideas in the domain of algorithm-based fault tolerance developed in the mid-80s for signal processing and matrix computations can be applied to a vast domain of circuits and systems in electrical engineering; from digital and analog filters to complex nonlinear autonomous control systems. The key insight is that electrical systems can be fundamentally represented by linear and nonlinear differential equations with equivalent matrix representations. These representations can be encoded with extra check states that bear a known relationship with all the observable states of the system independent of the system driving inputs. By checking for the validity of this relationship, errors can be detected and mitigated in real-time with near-zero latency with minimal hardware overhead. The broad vision of the proposed methodology is illustrated with examples from different electrical engineering domains.

In the past, techniques for error detection in linear digital and analog circuits using checksum codes have been developed and shown to be highly efficient. While error detection is a solved problem, error correction has proved to be difficult due to the time and area overheads involved in diagnosing failed system states and correcting them in real-time. To solve the correction problem, real-time probabilistic correction mechanisms have been proposed for digital circuits that correct for state errors in a probabilistic manner, circumventing the process of accurate error diagnosis. Such a technique is difficult to apply to continuous-time analog circuits without altering the analog transfer function, due to the nature of error feedback mechanisms involved. However, switched-capacitor circuits offer intrinsic advantages; they replicate analog continuous-time behavior while retaining the benefits of a digital clock. In this work, we show how errors in switched-capacitor circuits can be detected and corrected, using probabilistic correction algorithms, by taking advantage of the separation in time afforded by the use of a digital clock between error-free and error-affected clock cycles of the circuit. By probabilistically correcting errors in real-time before the onset of future clock cycles, the advantages offered by digital clocks are exploited to deliver high-fidelity analog performance in switched-capacitor filters resulting in significant SNR benefits at low cost.

Future 5G wireless systems will deploy massive MIMO systems with large numbers of transmit and receive antennas and novel RF transceiver architectures that admit RF beamforming. Such systems will need to be designed with built-in test and post-manufacture self-tuning capability for yield enhancement and in-field tuning. A key issue is the lack of observability into internal circuit nodes due to the convergence of multiple RF beamforming chains into a combined baseband signal and the need to decouple individual RF chain behaviors from combined baseband signals. A second problem is that of testing and tuning as many RF chains in parallel as possible across a diverse range of specifications and modes of operation (beam steering angles) using optimized test stimulus. The interdependence between phase shift and gain of phase-shifter/amplifier configurations complicates the latter. Also, in relation to SISO/MIMO omnidirectional systems, large numbers of tuning knobs are involved. To solve the above, we propose novel algorithms for parallel testing and tuning of massive MIMO beamforming systems. Machine learning assisted coarse tuning is first performed followed by a fine-tuning procedure utilizing gradient descent. Tuning for EVM and signal-to-interference ratio is performed under power constraints. Simulation results prove the viability of the proposed techniques.

A large class of real-time circuits and systems can be expressed in linear state variable form. Of particular interest are systems with sensors and actuators that can degrade over time or circuits that can suffer from parametric deviations due to electrical degradation. In the past, multiple checksum codes have been used for error detection and correction in linear systems. In this research, it is shown for the first time that under multi-parameter failures (variations), the transient checksum response (single checksum) to a system contains multi-parameter diagnostic information about the parametric failure. In other words, when a single checksum transient response is time-sampled, the resulting sampled values can be mapped to the critical parameters of the system that affect its performance under multi-parameter variations. The resulting information can be used to rapidly actuate adaption of relevant linear control mechanisms for the system (e.g. PID control) in order to restore system performance with very low correction latency. We make a case for this new “checksum observer” paradigm using motors, generators and a simple biquadratic filter. Preliminary results are presented and demonstrate the viability of the proposed ideas.

Soft errors resulting from encoding video sequences on unreliable hardware can create significant artifacts in decoded video sequences, contributing to extreme video quality degradation. Modern systems are required to operate under increasingly challenging constraints, including smaller feature sizes and lower operating voltage, increasing the likelihood of soft errors in the video encoding hardware. These conditions are of particular concern for energy-limited battery-operated systems since they may be required to operate in nonideal environments and/or continue operating with a practically depleted energy source. The proposed parallel independent signature processing design performs error detection and mitigation in video encoding hardware, enabling a graceful degradation of quality when encoding by using unreliable hardware. The effects of soft errors are minimized by preventing the error propagation normally associated with errors in encoded video sequences. This allows for the recovery of quality when errors are present in the video encoding system. Conventional video encoding techniques are designed to handle worst case error rates by increasing gate sizes and/or increasing the operating voltage of the system. Such designs have error-rate limits, and when these limits are reached, the systems tend to fail catastrophically, resulting in an unrecoverable signal. The proposed design allows for single upset events to translate into single transient artifacts in a decoded video sequence.

We present a methodology for algorithmic generation of test signals for the detection and diagnosis of a variety of short and open-circuit defects in analog circuits. Prior algorithms have focused on test generation for known short or open defect values. This places the burden of failure coverage on accurate analysis of observed defects in known failed parts at high cost. In this work, we optimize the test stimulus to detect theweakestshorts and opens in analog circuits using a concurrent stimulus and defect value optimization algorithm. Since the defect value itself is an optimization parameter, the responses of nonlinear circuits corresponding tomultiple defect valuesare considered as opposed to asinglelinearized representation corresponding to a fixed defect value as in the existing state of the art. The algorithm produces a test stimulus along with the values of the weakest shorts and opens that the stimulus can detect (the locations of the defects are specified to the algorithm). These values are determined by the design of the analog circuit itself and therefore subsume all specified detectable defects for the circuits concerned. Experimental results show the feasibility of the proposed approach on selected test cases and defect sets.

Physically Unclonable Function (PUF) circuits are designed to provide part-specific responses that are random across different copies of the circuit by exploiting the unavoidable process variations in nanometer scale fabrication. This property can be used as an important building block in security and cryptographic applications including key generation and challenge-response authentication. A major problem, however, is to ensure PUF response stability and reliability in the presence of circuit and environmental noise. SRAM based PUFs are most promising in this regard but still require extensive output error correction because the response of many cells in the memory array is not consistent. Unfortunately, all such "weak" cells cannot be determined in advance to allow their unstable responses to be masked out. In this paper we present a new SRAM PUF design that allows all the unstable weak cells to be reliably identified over the full range of operating conditions including temperature, electrical noise, and aging. By using the remaining "strong" cells, each instantiation of our SRAM PUF provides the same consistent and repeatable response every time it is challenged, without any need for error correction. Experiments reported here show that relatively few (of the order of 10%) SRAM PUF cells are truly stable in the presence of realistic circuit noise; in addition to the expected noise level, this number also depends on the random variability in the manufacturing process. Our simulation results show that the new SRAM PUF can be designed to maintain good robustness against any level of expect circuit and environmental noise, and is resilient to aging.

The Kalman filter is a versatile tool used in control and signal processing systems to predict statistically significant data from noisy measurements. In many practical control systems, not all the system states are directly controllable and observable. From noisy measurements of a limited subset of the observable system states, the Kalman filter predicts the mean values and covariances of the complete set of continuously evolving system states using specialized matrix arithmetic. Our goal is to detect errors in any underlying arithmetic computation (e.g. addition/multiplication) involved in the operation of the Kalman filter. While prior linear state checksum methods can be used to detect errors in a subset of the matrix operations of the Kalman filter, they do not suffice for detecting errors in the majority of calculations involved in determining the state covariances. To solve this problem, we develop the notion of statistical state covariance checks. Two applications of a Kalman filter, a trajectory tracking system and a linearized control system for an inverted pendulum are used to demonstrate the proposed approach. A simple state restoration approach is used to compensate for detected errors allowing the complete system to tolerate errors as and when they affect system operation.

The rapid proliferation of sensor networks and robots in a wide range of societal applications has focused renewed attention on error-free operation of their underlying signal processing and control functions for reasons of safety and reliability. While real-time error detection in linear systems has been investigated in the past, error detection in nonlinear control functions has largely relied on implementing redundancy in components, units, or subsystems resulting in excessive area/performance overheads. In this paper, we introduce a realtime error detection methodology for nonlinear control state space systems that uses mapped predictive check states for detecting sensor and actuator malfunctions and transient errors in the execution of the control algorithm on the underlying processor. In our approach, the check state at time t bears a known relationship with the corresponding states of the nonlinear system. This check state can also be predicted from knowledge of the prior system states and inputs using nonlinear mappings. Consistency between the prior known relationship and its predicted value above, is used to check for errors in system function. We demonstrate the proposed approach on two test cases - a classical nonlinear inverted pendulum balancing problem using a moving cart and a nonlinear sliding mode controller driven electromagnetic brake-by-wire (BBW) system. Simulation results show the effectiveness of the proposed approach for detecting degradation of the sensor and actuator functions and soft errors in the execution of the control algorithms.

In the modern mixed-signal SoC design cycle, designers are frequently tasked with detecting and diagnosing behavioral discrepancies between design descriptions given at different levels of hierarchy, e.g. behavioral vs. transistor level descriptions or behavioral/transistor level descriptions vs. fabricated silicon. One problem is detection, to determine if behavioral differences between design descriptions exist. If such differences (anomalies) are detected, then diagnosis is concerned with identifying the module in a hierarchical design description of the system that is most likely the root cause of the anomaly (typically under the constraint that only the primary outputs of the top-level hierarchies are observed. Previously proposed machine-learning classifiers require prior knowledge about the kinds of likely design errors typically encountered. In this work, we present a novel technique for the algorithmic foundation of circuit diagnosis predictions which does not require any assumptions about the nature of design errors. Our method employs iterative and alternate on-the-fly test generation and least-squares fitting of embedded low-order nonlinear filters to produce a best-guess estimate of the root cause of the anomaly. Experiments are conducted on two test vehicles, an RF transceiver and a phase-locked loop, several bug models are implemented, and the system's diagnosis predictions are analyzed.

The test generation problem for analog/RF circuits has been largely intractable due to the fact that repetitive circuit simulation for test stimulus optimization is extremely time-consuming. As a consequence, it is difficult, if not impossible, to generate tests for practical mixed-signal/RF circuits that include the effects of tester inaccuracies and measurement noise. To offset this problem and allow test generation to scale to different applications, we propose a new approach in which FSM models of mixed-signal/RF circuits are abstracted from hardware measurements on fabricated devices. These models allow accurate simulation of device behavior under arbitrary stimulus and thereby test stimulus generation, even after the device has been shipped to a customer. As a consequence, it becomes possible to detect process shifts with fine granularity and regenerate tests to adapt to process perturbations in a dynamic manner without losing test accuracy. A complete methodology for such adaptive testing of mixed-signal/RF circuits is developed in this paper. Simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.

The correct operation of transducers such as electric motors, is becoming increasingly important in autonomous systems that depend on the reliability of the underlying electronics to deliver Quality of Service to the end customer. In this paper, a methodology for detecting errors in DC motor operation and adapting its control parameters to compensate for the same using continuous linear checksums, is developed. The approach is different from prior application of checksum codes to analog circuits and servomotor systems, in that none of the states of the DC motor are directly controllable. Accordingly, from measurements of the observable states of the system, the control law for the motor is modified almost instantaneously, to recover motor performance in the most optimal manner possible in the presence of parametric deviations due to wear and tear. We focus on wear out susceptible electromechanical anomalies such as loss of torque due to increased ballbearing friction, etc. Simulation results supported by a hardware prototype support the viability of the proposed error detection and compensation methodology.

In this paper, a novel built-in tuning technique to compensate for process variability-induced imperfections in RF circuits is proposed. The yield improvement methodology proposed is a generic and self-contained tuning method that does not require a digital signal processor as in prior software-based methods or the use of a tester. The technique uses digital logic that can be synthesized on-chip along with the analog/RF tuning circuitry to performing self-tuning. An optimized digital bitstream (stimulus) is used to stimulate the RF device, and the response of the device is downconverted to the low-frequency domain using a sensor. The resulting signal is mapped to a digital signature, in such a way that the Hamming distance between the observed and the reference signatures represents the degree by which the device specifications differ from the nominal specifications. A logic-driven algorithm is used to minimize this Hamming distance to optimize multiple RF specifications concurrently. The presented methodology incurs minimal area overhead, and the tuning time is in the order of milliseconds. Results obtained by tuning the power amplifier of a 2.4-GHz transmitter show up to 16% yield improvement. To validate the proposed yield improvement concept on hardware, results obtained from experimentation on an industrial transmitter are presented.

In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability of an analog push-pull amplifier under process variations. A differential amplifier architecture is proposed with digital interfaces to allow the PUF to be used in digital as well as mixed-signal SoCs. A key innovation is digital stimulus engineering for the analog amplifier that allows 2X improvements in the uniqueness of IC signatures generated over arbiter-based digital PUF architectures, while maintaining high signature reliability over +/- 10 % voltage and -20 to 120 degree Celsius temperature variation. The proposed PUF is also resistive to model building attacks as the internal analog operation of the PUF is difficult to reverse-engineer due to the continuum of internal states involved. We show the benefits of the proposed PUF through comparison with a traditional arbiter-based digital PUF using simulation experiments.

This paper describes an ATE extension module that enables a low-cost test system to be applied to advanced (multi-GHz) memories. The target application is for testing memories with data rates above 3.2Gbps. The test module uses state-of-the-art FPGAs for economical autonomous pattern synthesis and comparison under the high-level supervision of a low-cost “host” test platform (ATE). The FPGA logic capabilities are complemented by custom 4-channel “pin electronics” (PE) modules with I/O performance comparable to advanced ATE. The PE modules provide input/output/bidirectional signal conditioning, including amplitude, format, timing, and pre-emphasis, and a “shadow sampler.”

Real-time systems for wireless communication, digital signal processing and control experience a wide gamut of operating conditions (signal/channel noise, workload demand, perturbed process conditions). As device bandwidths expand, it becomes increasingly expensive, from a power consumption and reliability perspective, to operate such real-time systems for worst-case (static) performance requirements. In contrast, it is attractive to design algorithms, architectures and circuits that are power-performance tunable and can adapt dynamically, via self-learning techniques, to the requirements of system-level applications for extended battery usage and device lifetime. Such future systems will feed application level demands to the underlying algorithm-architecture-circuit design fabric through built-in sense-and-control infrastructure (hardware, software). The sense functions assess instantaneous application level demands (e.g. throughput, signal integrity) as well as the performances of the individual hardware components as determined by manufacturing process conditions. The control functions actuate algorithm-through-circuit level tuning knobs that continuously trade off performance vs. power of the individual software and hardware modules in such a way as to deliver the end-to-end desired application level Quality of Service (QoS), while minimizing energy/power consumption. Application to wireless communications systems, digital signal processing and control algorithms is discussed.

Soft errors due to alpha particles, neutrons and environmental noise are of increasing concern due to aggressive technology scaling. While prior work has focused mostly on error resilience of linear signal processing algorithms, there is increasing need to address the same for nonlinear systems used in emerging applications for sensing and control. In this paper, a new approach for detecting errors in nonlinear digital filters is developed that does not require full duplication of all the nonlinear operations in the filter. First, a checksum of the linear least squares fit to the nonlinear function of the filter is derived that is ideally zero when the filter nonlinearities are not excited. Next, in residue prediction, linear predictive codes are used to predict the nonzero checksum error values that result exclusively from filter nonlinearity excitation. This allows fine granularity soft error detection at low hardware cost. Simulation experiments on a nonlinear Volterra filter prove the viability of the proposed concurrent error detection methodology.

While the notion of self-awareness has a long history in biology, psychology, medicine, engineering and (more recently) computing, we are seeing the emerging need for self-awareness in the context of complex Systems-on-Chip that must address the often conflicting requirements of performance, resiliency, energy, cost, etc. in the face of highly dynamic operational behaviors coupled with process, environment, and workload variabilities. Unlike traditional Systems-on-Chip (SoCs), self-aware SoCs must deploy an intelligent co-design of the control, communication, and computing infrastructure that interacts with the physical environment in real-time in order to modify the systems behavior so as to adaptively achieve desired objectives and Quality-of-Service (QoS). Self-aware SoCs require a combination of ubiquitous sensing and actuation, health-monitoring, and self-learning to enable the SoCs adaptation over time and space. This special session targets self-learning and self-awareness in two domains. The first one is a self-learning runtime reliability prediction approach by reusing Design-for-Test (DfT) infrastructure. The other one discusses real-time systems and applications to wireless communication, signal processing and control.

The quality of a communication link is commonly indicated by signal to noise/interference ratio and affected by noise and interference variance. To ensure a power efficient adaptive OFDM system's performance, the system needs to be tested against various channel conditions. Conventional algorithms and experiments assume that the noise and interference density stays constant over the OFDM frequency band but in reality the communication link often populated with both white noise and interference that results an uneven impact on OFDM spectrum. To create such channel condition, an up-conversion is commonly used. However, due to the non-linearity of the mixer, the up-converted interference is always distorted. The proposed method uses a modified higher-than-Nyquist-rate RF signal generation algorithm to minimize the distortion of generated interference within a pre-defined output bandwidth. Both concept validation and experimental measurement have been conducted to prove the effect of proposed method.

Modern radio front ends are required to operate over diverse channel conditions requiring the incorporation of significant performance overheads into their design. This results in significantly higher power consumption over most of the operational period since the worst case channels are not statistically prevalent. Adaptive systems solve this problem by adapting the performance and power consumption depending on channel conditions. In this paper, it is demonstrated that depending upon the throughput requirements of the system multiple low-power adaptation modes can be designed. These modes ensure either highest throughput operation or lowest energy-per-bit operation. The operation of these modes is demonstrated in simulation using multiple-input-multiple-output (MIMO) receiver and transmitter front ends. Subsequently, the concepts are demonstrated in hardware for both MIMO and single-input-single-output front ends.

Integration of RF circuits in deeply scaled CMOS technologies and severe process variation in those technology nodes result in poor manufacturing yield. A post-manufacture tuning approach for yield improvement of RF systems is developed in this paper that uses hierarchical behavioral models of the RF systems. The proposed method first determines module-level performances from the system-level response (signature) to an applied test using top-down model diagnosis. Then, constrained optimization is performed to determine the best module-level tuning parameter values that satisfy system-level specifications (bottom-up analysis) in a power-conscious manner. Both top-down and bottom-up analysis techniques are supported by hierarchical RF behavioral models. The relationship between module-level tuning parameters and module-level performance metrics changes from instance to instance depending on amount of process variation and this factor is included in the proposed tuning procedure. A key benefit of the proposed approach is that only a single-test application is needed at a fixed number of tuning knob settings resulting in reduction in tuning time. The efficiency of the proposed technique is demonstrated using simulation results and hardware experiment.

In this brief, an optimized test stimulus generation technique is proposed for model parameter computation-based diagnosis and testing, which can provide a very compact deterministic test signal and results in significant reduction in test time. The proposed test stimulus generation algorithm maximizes the accuracy with which a nonlinear solver can determine RF transceiver model parameters from raw downconverted test response data. The simulation results show that using optimized test signals, a comprehensive range of model parameters can be computed accurately using a single data acquisition. Data from experiments performed on a hardware prototype are shown to validate the proposed methodology.

Incoherent undersampling-based waveform acquisition provides a low-cost test setup for characterizing high-speed systems. A periodic waveform reconstruction using incoherent undersampling remaps time indices of samples using the modulus of the suspected period of the signal, effectively folding the signal into a time window equal to one period. The major cost and accuracy limitations of the reconstruction technique arise from estimation of the waveform period. Multiple cost functions have been proposed to estimate the period, including frequency domain metrics, which are computationally intensive. In this paper, we propose a new time domain zero-crossing (ZC)-based metric, where the metric gives the number of ZC in the reconstructed waveform for an assumed period of the waveform. The reconstruction technique is also extended to beyond the track-and-hold amplifier bandwidth using a novel test setup combining the incoherent undersampling with multichannel bandwidth interleaving.

The advent of sensor networks, robots, autonomous vehicles and the smart grid have made the dependability of circuits and systems that control them critical to society and national defense. While significant advances in the design of linear and nonlinear control systems have been made to allow modes of operation not possible in the past, the problem of resilience to errors induced by hostile operating environments remains largely unexplored even though the probability of such errors occurring during real-time operation has increased. In this talk we propose mechanisms for detecting transient errors in control systems and circuitry as well as diagnosing and correcting for their effects on overall system operation. It is shown how real-number checksum encodings of circuit function can be used to detect and correct errors in the plant and feedback subsystems of linear control systems. Applications to signal processing and control algorithms are described. It is shown how errors in motor control electronics can be detected and corrected using the proposed methodology. Finally, extensions to nonlinear control systems are presented.

Insertion of malicious Trojans into outsourced chip manufacturing generally results in increased capacitances of internal circuit nodes that have been tapped for node controllability and observability by malicious circuitry. Current path delay measurement and side channel Trojan detection techniques are unable to detect Trojans that present low loading to such tapped circuit nodes, especially in the presence of large manufacturing process variations. In this paper, a high-resolution Trojan detection method for digital logic based on pulse propagation is developed. The method exhibits 25X -- 30X higher diagnostic resolution (ability to measure small capacitive loads on internal circuit nodes) as compared to current path delay based Trojan detection techniques in the presence of significant manufacturing process variations. Further, a key benefit is that theoretically, as opposed to path delay measurement based methods, the diagnostic resolution of the test approach is independent of circuit logic depth over and above the benefits already mentioned above. Test methods and test infrastructure compatible with existing scan based techniques are described. Simulation results are presented to prove the viability and effectiveness of the proposed Trojan detection scheme and especially for circuits with large logic depths (35-70 gates) suffering from worst case process variation effects.

Analog checksum based fault tolerance for linear circuits has been proposed in the past but remains a theoretical artifact due to the high cost and complexity of error compensation while other redundancy based methods have prohibitive overheads. To resolve this, new low cost error compensation methods for widely used linear analog circuits are developed in this research. Trial and error based compensation learning methods combined with the use of less than minimum distance codes are used for failure tolerance. This results in significant hardware savings over prior correction schemes with minimal increase in error correction latency. It is shown how dual failures in analog circuits, not possible with existing techniques, can be compensated using the proposed fault-learning approach.

Prior research has established that dynamically trading-off the performance of the RF front-end for reduced power consumption across changing channel conditions, using a feedback control system that modulates circuit and algorithmic level "tuning knobs" in real-time, leads to significant power savings. It is also known that the optimal power control strategy depends on the process conditions corresponding to the RF devices concerned. This complicates the problem of designing the feedback control system that guarantees the best control strategy for minimizing power consumption across all channel conditions and process corners. Since this problem is largely intractable due to the complexity of simulation across all channel conditions and process corners, we propose a self-learning strategy for adaptive MIMO-RF systems. In this approach, RF devices learn their own performance vs. power consumption vs. tuning knob relationships "on-the-fly" and formulate the optimum reconfiguration strategy using neural-network based learning techniques during real-time operation. The methodology is demonstrated for a MIMO-RF receiver front-end and is supported by hardware validation leading to 2.5X power savings in minimal learning time.

Analog circuits are sensitive to signal aggressions and power supply noise, crosstalk coupling and alpha particle strikes can cause significant degradation of circuit's SNR. This research proposes a novel approach to real-time transient error and induced noise cancellation in linear analog circuits using analog checksums. It is based on the use of state space representations of analog filters and is a significant advancement over prior research that addressed only hard parametric deviations. A key innovation is the use of less than minimum distance checksum codes for error detection and correction using real-time learning of the likely source of transient errors and noise within the analog circuit. By running a simple hardware-directed search algorithm, the circuit “learns” how best to compensate for the injected signal disturbances with low overhead under the assumption that the source of the injected errors/noise and the error/noise statistics are stationary over time. Successful simulations and preliminary experimental results demonstrate almost complete compensation of injected noise, therefore validating the proposal.

As communication data rates increase, wideband signals are being increasingly used to accommodate high rates of information transmission. Acquiring and characterizing the time domain waveform of such signals requires high measurement system sampling rate and wide input bandwidth and is thus, expensive. A key problem that drives up the cost of traditional bandwidth interleaved data acquisition systems is the need to synchronize the input signal (periodic) with the sampling clock as well as the oscillator inputs to all the mixers in the band interleaved architecture. This synchronization problem is complicated at multi-GHz frequencies and increases overall design cost. In this paper, we propose a low-cost band-interleaved architecture that uses: (a) incoherent undersampling to acquire the signal across the frequency bands of the band-interleaved system and (b) does not require any mutual synchronization between the input signal, the undersampling clocks and the mixing signals (local oscillators) of each frequency band in the band-interleaved system. The reconstruction is achieved through back-end spectrum analysis and use of signal processing algorithms that compensate for the lack of synchronization. The proposed technique is supported by hardware validation experiments.

This paper proposes a self-tuning architecture for buck converters based on a modified alternative “safe” testing approach. It avoids voltage spikes caused by conventional full load testing and provides measurements with strong statistical correlation with the DUT's specifications. The measurements are sampled by a 5-bit ADC and analyzed by on-chip resources for evaluating the DUT specifications and predicting the corresponding values of buck converter tuning knobs to compensate for process variations when standard performances are not met. Thus, the proposed methodology enables self-test and self-tuning of buck converters during production test without the risk of DUT damage during standard production test. The causes of voltage spikes during conventional full load test are discussed both analytically and numerically and the working mechanism of an alternative test procedure is developed. This proposed technique is demonstrated through both simulation and hardware validation experiments.

As RF design scales to the 28nm technology node and beyond, pre-silicon simulation and verification of complex mixed-signal/RF SoCs is becoming intractable due to the difficulties associated with simulating diverse electrical effects and design bugs. As a consequence, there is increasing pressure to develop comprehensive post-silicon test and debug tools that can be used to identify design bugs and improve modeling of complex electrical nonidealities observed in silicon. Often, it is not known a-priori what these bugs are and how they can be modeled, significantly complicating the debug process. In this research, a new atomic model learning approach is proposed that uses supervised learning techniques to diagnose design bugs and learn unknown module-level behaviors. Nonideality modeling artifacts called model atoms are inserted into different nodes of the design signal flow paths to learn unknown behaviors along those paths. Under the assumption that the design bug is localized, it is shown that the source of the bug can be identified with high resolution even when the nature of the bug is unknown. The method has been applied to a conventional wireless as well as a polar radio transmitter and key results that demonstrate usefulness and feasibility of the proposed approach are presented.

As an important factor for long-term jitter in clock synthesis and distribution, reference spurs result from circuit mismatch and nonlinear effects that induce periodic perturbations in phase-locked loops (PLLs). In this paper, a PLL with built-in static phase offset (SPO) detector and charge pump current trimming for self-calibration circuits is proposed. By adjusting the charge pump current ratio determined by an SPO detector, minimum and maximum improvements of 12dB and 22.99dB in reference spur suppression can be achieved. The best improvement reduces the integrated jitter by 10% over a 10kHz to 10MHz bandwidth. The technique is demonstrated for a PLL output frequency from 400 MHz to 1 GHz. The ring oscillator based PLL is designed with 200 KHz bandwidth and 70 degree phase margin. Measurement results from chips across different corners are provided to verify the calibration technique.

This paper proposes a new multi-channel testing architecture for high-speed eye-diagram. The proposed architecture reconstructs the eye-diagram of a multi-Gbps bit pattern with the combination of pin electronics and reconstruction algorithms. A scalability of the test system significantly increases in behalf of a monobit receiver and its designated reconstruction algorithm. A novel reconstruction algorithm using monobit receiver and subsampling clock enables the test system to monitor the signal quality in low-cost. The proposed architecture is implemented and demonstrated in a hardware prototype. Experiment with the hardware prototype shows that an eye-diagram of 3.2Gbps bit pattern can be reconstructed within sub-picosecond resolution by the proposed method with subsampling clock (below 100MHz).

This paper presents a novel alternative “safe” test method for line and load regulation specifications of hysteretic controlled switching power converters. These specifications have not been tested in production before because the conventional measurement techniques lead to huge voltage spikes during switching transients. Those voltage spikes are caused by energy accumulation from parasitic inductances of ATE interface board to input capacitance of the device under test (DUT) and can damage DUT's internal circuitries. The proposed alternative test approach offers a “safe” manufacturing test of load/line regulation specifications of hysteretic controlled switching power converters through a carefully altered feedback circuit and a current-limited load. Through injecting the altered feedback circuit with a carefully crafted stimulus, the load and line regulation specifications of DUT are accurately predicted. This test approach is facilitated by the use of a DAC for stimulus generation and ADC for DUT response capturing. Both simulated data and hardware measurements are used to demonstrate the viability of the proposed ”safe”testing method.

This paper presents a process-variation tolerant, continuously channel-adaptive wireless front-end architecture and related adaptation algorithms to allow a radio-frequency transceiver to function with minimum power at all channel conditions and manufacturing process corner. Current wireless transceiver front-ends are designed for worst case channel conditions and a limited degree of post manufacture tuning is performed to compensate for process variations. It is shown how the proposed architecture can result in significant power savings over current practice without compromising system-level bit-error rate (while keeping the end-user experience unaffected). In contrast to traditional wireless circuits with limited tunability, such a zero-margin design is achieved by close loop adaptation of the wireless front-end circuits to ensure that they only consume the minimum power and deliver just enough performance (and not any more) for any channel condition. The adaptation methodology is applied to a WLAN receiver design and hardware measurement data for an adaptive receiver is presented showing a > 3 × power improvement under best case channel conditions.

In the recent past, there has been steady growth in the data transfer rate of modern digital serial communication systems. Consequently, accurate characterization of high-speed signal transmission lines is necessary for ensuring high signal integrity. Time domain reflectometry (TDR) has been widely used in prior research to characterize high speed interconnect. The accuracy of the characterization depends on the sampling rate and the slew rate of the TDR input excitation signal. At high speeds it is not always possible to deliver "perfect" (impulse/step) TDR stimulus. In this paper, an algorithm is presented to compensate for the inherent distortion in nonideal TDR stimulus to improve the accuracy of interconnect characterization. The algorithm is applied to the problem of micro strip transmission line characterization for identifying discontinuities in signal interconnect. Hardware measurements validate the effectiveness of the proposed technique.

Incoherent undersampling provides a low cost solution for wideband periodic waveform acquisition without the requirement for synchronization with the source clock. The bandwidth of a traditional incoherent undersampling based test setup is limited by the the bandwidth of the track and hold amplifier. In this work, a test setup is proposed combining incoherent undersampling and bandwidth interleaving to break the bandwidth barrier of the track and hold amplifier. The high frequency components of the signal waveform beyond the track and hold bandwidth are down converted using mixers and undersampled. While bandwidth interleaved frequency domain signal reconstruction techniques have been proposed before, this is the first time that fast time domain reconstruction techniques are used for periodic waveform reconstruction of wideband signals in the absence of any synchronization between the test signal and the tester oscillator/sampling clock over multiple frequency bands by choosing the local oscillator frequency to be a multiple of the sampling frequency. The periodic test signal waveform is acquired over multiple channels each covering only part of the total bandwidth of the signal. Feasibility of the proposed technique is shown through simulation and hardware results.

Phase-locked loops are used to synthesize frequency sources for RF conversion and IO clocks for data synchronization, and serve as core building blocks for communication systems. Consequently, testing of PLL loop performance is critical for guaranteeing the reliability of the underlying communication systems. In this paper, a testing method based on loop triggering and use of low-cost built-in analog sensors (small number of transistors) to accurately predict phase-locked loop dynamic parameters is proposed. The sensors are designed in such a way that the sensor responses show strong statistical correlation with the PLL parameters being tested. Accordingly, supervised learners are "trained" to predict the required PLL parameters from the observed sensor response. A PLL is designed and simulated in closed loop over PVT corners in order to validate the testing mechanism. Parameters including charge pump current, VCO gain, bandwidth, phase margin, and locking time are predicted accurately and concurrently over these PVT corners to prove the viability of the proposed test method.

This paper proposes a novel test method for the line and load regulation specifications of switched mode power converters (SMPCs) using alternative safe measurements. These specifications are not tested for many power converters because they cause voltage spikes under full load conditions on the tester that can damage the converter circuitry. To prevent damage to the DUT during manufacturing test, we propose a modification of the power converter load during test application. Optimized low cost tests are applied to the converter under low load current conditions, allowing accurate prediction of the closed-loop load and line regulation specifications (that require high load current) from the modified test procedure without the possibility of any damage to the DUT. The test approach is facilitated by the use of two sensors that allow the line and load regulation specifications of the converter to be predicted accurately from the proposed alternative test measurements. Simulation data and measurements from a hardware prototype are used to demonstrate the viability of the proposed safe testing approach.

Modern MIMO RF transceiver systems are designed to operate reliably under diverse channel conditions leading to incorporation of significant performance margins in RF transceiver systems. In general, across dynamically varying channel conditions, the fidelity of the RF front end devices can be traded-off against power consumption without compromising system-level BER limits. In this work such a real-time performance vs. power consumption modulation of RF front-end devices in MIMO systems is demonstrated. Through a multi-dimensional optimization technique, power-optimal configuration of the front-end for varying channel conditions are created. Additionally multiple low-power operating modes for the MIMO system are proposed depending on the performance metric (data rate or energy-per-bit) that need to be optimized for different applications.

Jitter measurement is an essential part for testing high speed digital I/O and clock distribution networks. Precise jitter characterization of signals at critical internal nodes provides valuable information for hardware fault diagnosis and next generation design. Recently, incoherent undersampling has been proposed as a low-cost solution for signal integrity characterization at high data rate. Incoherent undersampling drastically reduces the sampling rate compared to Nyquist rate sampling without relying on the availability of a data synchronous clock. In this paper, we propose a jitter decomposition and characterization method based on incoherent undersampling. Associated fundamental period estimation techniques along with properties of incoherent undersampling, are used to isolate the effects of periodic and periodic crosstalk jitter. Mathematical analysis and hardware experiments using commercial off-the-shelf components are performed to prove the viability of the proposed method.

A low cost methodology for simultaneous testing and tuning of multiple chains of MIMO-OFDM wireless transmitter for system-level specifications is presented. Bandwidth-partitioned test stimuli enable the determination of the behavioral characteristics of the different chains of the RF transmitter using a one-time data acquisition. The determined behavioral characteristics of the transmitters are then correlated to system-level specifications in the simulation environment. Using the test setup, a power conscious system-level tuning approach for yield improvement is developed for tuning of parametric deviations. A yield improvement of 20% is obtained using the proposed methodology. Finally, an adaptive tuning approach is presented for those devices that face increased reliability risks/power-budget violations due to the excessive power consumption caused by post-manufacturing tuning. The tuning methodology achieves new performance metrics for these devices that attempt to maximize the conditions under which the device operates. Significant improvement in yield is obtained using the adaptive tuning methodology. Preliminary hardware validation of the proposed methodology using off the shelf components is performed.

In the recent past, there has been a proliferation of complex control problems in sensor network design, multi-agent systems such as autonomous vehicles and robotics, to name a few. While prior research has focused on the design of optimal controllers for real-time systems, in the future it will become increasingly difficult to perform periodic maintenance of such systems due to their mobile and autonomous nature. Moreover, in safety-critical real-time applications it will become increasingly necessary to perform real-time monitoring of the plant as well as its controller functions for reasons of reliability and safety. In this paper, we develop, for the first time, a theory for implementing low-overhead and high coverage detection of transient errors and permanent faults in linear control systems consisting of the plant and its controller using analog checksums. The approach is demonstrated on a servo-motor control problem. It is shown that small parametric perturbations as well as transient errors are detected in real-time using the proposed checking methodology.

Integrated power amplifiers in RF communication systems suffer from efficiency reduction with power back-off, performance degradation due to process variation and reliability issues due to high signal levels. Design of a dynamically adaptive class-E switching power amplifier with duty cycle modulation is proposed in this paper. It uses an LC tuning circuit with a variable capacitor that improves efficiency, reliability and process variation tolerance compared to traditional class-E power amplifiers. The proposed power amplifier is designed in 65nm CMOS process for 2.4 GHz carrier frequency. Simulation results show significant increase in efficiency at lower power levels, reduction in peak drain voltage, which improves reliability, and mitigation of process variation effects.

Devices manufactured in 20 nm and smaller geometry technologies will potentially be very large by today's standards, they will also have new characteristics implied by things like process variability and adoption of FinFET transistors. The industry has cumulatively adopted more and more sophisticated fault models that use timing as well as layout information. There is a growing body of experimental data showing it is still insufficient. The next area of focus will be the quality of test. Cell-aware test is one of the most promising approaches developed over the last five years aimed at improving the quality of test while maintaining the efficiency of gate-level approach. This approach combines two levels of abstraction to provide trade-offs between accuracy and efficiency. The first step creates the cell-aware test library models. It starts with standard cell libraries and performs layout extraction. Realistic defects (bridges and opens) are injected into the SPICE netlist, and analog fault simulation is performed to determine the conditions under which the defects are detected. Those conditions are aggregated to create a compact and efficient representation of the libraries for ATPG done at the gate-level. Generation of library views for cell-aware test is performed only once for a given standard cell library. The final cell-aware ATPG generates the high quality test patterns based on the cell-aware library views. This guarantees that the investment in gate-level ATPG infrastructure could be efficiently utilized. The technology has been used on a number of high-volume industrial designs. The experimental data show a significant increase of defect coverage and the corresponding improvement of defect rate.

Reference spur is a nonlinear effect and important specification in PLL for long term jitter. Periodic events of reference clock create a static phase offset between signals. The finite phase offset comes from charge pump mismatch and layout asymmetry. This paper presents a built-in self-test (BIST) circuit applied for PLL static phase offset (SPO) estimation. The proposed circuit takes advantage of an integrator for time-to-voltage conversion (TVC). Along with comparators and counters, a BIST can be constructed for an estimation of mismatch ratio down to 1% over process corners in simulation (10 psec for lnsec pulse width). The calibration can be operated in a closed-loop PLL with lock signal. Additional circuits including delay lines and non-inverting amplifiers are designed for fast calibration. The result shows at least 27 times faster detection speed can be achieved over process corners. The phase offset between PLL reference and feedback signal is essentially the duty cycle difference, and the test is also applied for duty cycle distortion. Related analysis and measurement are included.

This paper proposes a new method to reconstruct signal by a monobit receiver based on incoherent subsampling. The proposed method uses a time-variant threshold voltage for the monobit receiver to increase its amplitude resolution. By our methodology, the threshold voltage does not have to be synchronized with the input signal nor the sampling clock of the system. Hardware measurement with FPGA and high-bandwidth clocked-comparators shows that a low-cost multi-channel test is achievable by our method. The hardware measurement results show a square waveform and a sine wave waveform reconstruction.

With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels of integration, the tasks of both design and device validation is becoming increasingly complex. Post-silicon validation of mixed-signal/RF systems provides assurances of functionality of complex systems that cannot be asserted by even some of the most advanced simulators. We introduce RAVAGE (from “random;” “validation;” and “generation”), an algorithm for generating stimuli for post-silicon validation of mixed-signal systems. The approach of RAVAGE is new in that no assumption is made about any design anomaly present in the DDT; but rather, the stimulus is generated using the DUT itself with the objective of maximizing the effects of any behavioral differences between the DUT (hardware) and its behavioral model (software) as can be seen in the differences of their response to the same stimulus. Stochastic test generation is used since the exact nature of any behavioral anomaly in the DUT cannot be known a priori. Once a difference is observed, the model parameters are tuned using nonlinear optimization algorithms to remove the difference between its and the DUT's responses and the process (test generation→tuning) is repeated. If a residual error remains at the end of this process that is larger than a predetermined threshold, then it is concluded that the DUT contains unknown and possibly malicious behaviors that need further investigation. Experimental results on an RF system (hardware) are presented to prove feasibility of the proposed technique.

A low-cost linearity test methodology for high-resolution analog-to-digital converters (ADCs) is presented in this paper. Linearity testing of ADCs requires high-precision digital-to-analog conversion (DAC) capability, commonly 3-bit higher resolution than the ADC under test. Further, a large number of ADC output data samples must be collected making conventional histogram testing impractical for high-resolution ADCs with 18-24 bit precision. In the proposed test methodology, two low-precision and low-cost DACs are used to generate a high-resolution ADC test stimulus. Significant reductions in test cost and test time are achieved by using low-cost instrumentation and by making fewer measurements than required for conventional histogram test. A least-squares-based polynomial fitting approach is used to determine the transfer function of the ADC under test. The generated transfer function is used to compute the non-linearity of the ADC accurately. No assumption is made regarding the linearity of the lower precision signal generators (DACs) used in the testing procedure. Software simulations and hardware experiments are performed to validate the proposed test methodology.

Acquisition of periodic waveforms is an integral part of characterizing high speed system performance. Various techniques are used to reduce the equipment cost, dominated by the cost of the digitizer. Incoherent under-sampling provides an attractive solution for signal acquisition. However, due to the aliasing present in under-sampled signal and the windowing effects, high resolution spectral estimation is difficult. This is especially true when under-sampling is combined with techniques such as bandwidth interleaving to extend the bandwidth of the test setup beyond the track and hold bandwidth. In this paper we propose a high resolution spectral estimation technique and propose a new setup that combines incoherent under-sampling with the bandwidth interleaving without requiring a synchronization with the signal clock. This enables waveform acquisition with bandwidth greater than the sampling track-and-hold bandwidth.

Testing of adaptive analog/RF systems is challenging as any test procedure must ensure that the system adapts correctly to external perturbations (process, workload) without incurring the excessive test time associated with iterative tuning procedures. This problem is made worse by the increased number of adaptation settings (“tuning knob values”) and the requirement of measuring specifications at all of these settings. In this paper, a new test technique is proposed that allows the closed loop performance of the adaptation procedure to be predicted from a set of open-loop tests. The optimal knob settings where the system should be tested in open-loop are found using a gradient based search algorithm and optimized test signals are generated such that the error in performance prediction across different tuning knob settings is minimized. The results of these tests are then mapped to the performance of the adaptive system which is validated implicitly without incurring large testing and tuning costs. Simulation results and hardware measurement results prove the validity of the proposed technique.

Due to the use of scaled technologies, high levels of integration and high speeds of today's mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation of all electrical aspects of the design including the interfaces between digital and analog circuitry, coupling across power and ground planes, crosstalk, etc., across all process corners is very hard to achieve in a practical sense. The problem is expected to get worse as analog/mixed-signal/RF devices scale beyond the 45nm node and are more tightly integrated with digital systems than at present. In this context, a post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model. The corresponding error signature is then used to identify the likely "type" of electrical bug and its location in the design using nonlinear optimization algorithms. Results of trial experiments on RF devices are presented.

Modern RF circuits suffer from increased electrical degradation induced by electrical stress and thermal effects due to the high speeds of operation and the effects of technology scaling. Detection of such degradation is important, particularly in wireless basestations which must operate round-the-clock with high dependability. In this paper, a new approach for detecting degradation in RF transmitter systems using pilot symbols is proposed and is superior to prior algorithms because degradation can be monitored on a frame-to-frame basis independent of the data being transmitted. The response of the RF transmitter to known pilot symbols is captured at the output of the RF power amplifier using an envelope detector and is fitted to a third order transmitter model using a model-parameter solving algorithm. It is shown that the computed model parameters deviate away from their nominal values, exhibiting model anomalies once nonidealities due to electrical degradation start affecting transmitter behavior. The amount of the degradation is proportional to the magnitude of this deviation as measured by a distance metric and is easily computed using simple algorithms running on the baseband processor. Preliminary results indicate the feasibility and low cost of the proposed approach.

Earlier research has demonstrated that the power in a RF front-end can be traded off for performance in real-time to operate at the threshold of acceptable operation using a lookup table driven controller. Such a controller needs careful calibration and suffers from modeling inaccuracies which must be guardbanded during real-time operation resulting in "less than optimal" power consumption. In this work we propose a real time fuzzy noise-distortion control algorithm for low-power adaptation of the RF front-end to continuously changing channel conditions. As opposed to prior techniques, the proposed control algorithm handles adaptation to channel attenuation and fading as well as in-band and out- of- band interference, taking advantage of signal and interferer estimation techniques that are already incorporated in modern transceivers. In the proposed technique, the RF front-end controller automatically finds an optimal power-performance trade-off point in real-time across a large gamut of channel conditions. It is seen that about 23% savings in power consumption can be obtained over RF systems that are not capable of real-time adaptation.

In this paper, we propose a new algorithm to estimate the fundamental period (frequency) of a highspeed pseudo random bit sequence (PRBS) or multitone signal using incoherent subsampling. While incoherent subsampling suffers from spectral leakage due to the mismatch between the input test signal and the discrete Fourier transform (DFT) basis, the proposed algorithm efficiently resolves the spectral leakage problem using a back-end signal process. The approach requires incoherent digitization of the periodic sequence using at least two clocks running at different speeds. No additional hardware to synchronize the input signal frequency with the sampling clock frequency is needed. A new discrete frequency shifting approach for determining the period of the input signal is proposed that is computationally efficient. The signal reconstruction approach has been tested with experimental results.

Acquisition of wide bandwidth signals is a significant problem in manufacturing test due to the cost of test equipment driven by the use of high-speed sample and hold circuitry and difficulty in data-clock synchronization. We propose to combine frequency interleaved down conversion (to overcome the bandwidth limitations of sample and hold circuitry) with incoherent undersampling (to overcome data-clock synchronization and ADC speed issues) to design a low cost instrumentation for high speed signal capture. A novel signal reconstruction algorithm is developed along with a method for calibrating the effects of unknown delays in data acquisition hardware due to mismatch in signal path lengths on the reconstructed signal. Simulation results and preliminary hardware validation prove the feasibility of the proposed technique.

In this paper, a higher than Nyquist RF test waveform synthesizer with digital phase noise injection is proposed. The proposed system uses time-interleaved digital-to-analog converters (DACs) and associated digital signal processing algorithms to enhance the spectral image of the synthesized waveform in the high-order Nyquist zones by increasing the effective sampling rate and eliminating unwanted signals inside the bandwidth of interest. The generated spectral images are used as the primary output of the proposed system. The waveform synthesizer is capable of digitally controlling the phase noise characteristics of the output signal in the high-order Nyquist zones. In addition, it utilizes relatively low-cost off-the-shelf integrated circuits (ICs) for multi-GHz signal generation. In hardware validation, dual DACs operating at 2.5Gb/s (effective Nyquist rate of 5 Gb/s) are used to generate a signal centered at 3.2GHz (corresponding to a Nyquist rate of 6.4 GHz). In addition, controlled phase noise generation is demonstrated.

In this paper, we propose a wideband signal reconstruction scheme for testing high-speed pseudo random bit sequences (PRBSs) in the presence of jitter noise using incoherent sampling. The proposed approach exploits synchronous multirate sampling (SMRS) hardware and multicoset back-end signal processing algorithms. The SMRS hardware consists of multiple analog-to-digital converters (ADCs) whose sampling frequencies are synchronized with a common frequency reference and can be individually configured. The optimal sampling frequency of each ADC is chosen based on the input signal information and sampling hardware specifications. As compared to other sampling hardware used for multicoset signal reconstruction, the proposed approach uses less number of ADCs and does not require accurate sampling clock phase adjustment. In the digital signal reconstruction, the input waveform is reconstructed by the multicoset signal processing algorithms and the phase noise of each tone of the PRBS test signal is measured.

In this paper, we propose a new test response acquisition technique for high-speed devices-based on dual-frequency incoherent sub-sampling and sparse signal reconstruction. The proposed technique enables reconstruction of spectrally sparse wideband signals such as multi-tone signals and short pseudo-random bit sequences (PRBS) with enhanced time/frequency resolution as opposed to current methods. The sampling hardware utilizes dual analog-to-digital converters (ADCs) and dedicated sampling frequency synthesizers with a common frequency reference. As compared to other compressive sampling architectures [1], the proposed hardware architecture is easy to implement at low cost since it does not require accurate sampling clock phase adjustment or random timing generation. For digital signal reconstruction, the proposed technique requires less number of waveform samples than conventional equivalent-time sampling techniques. In addition, the use of an resolution-enhanced discrete Fourier transform (DFT) frame and basis pursuit algorithms minimizes spectral leakage of incoherently sub-sampled signals. This co-design of sampling hardware and signal reconstruction algorithms enables testing of spectrally sparse wideband signals with enhanced time/frequency resolution.

Error-vector-magnitude (EVM) is a system level specification that determines the overall modulation quality and exhibits strong correlation to the inherent nonidealities of a radio frequency (RF) system. In production testing, EVM tests incur significant cost due to the large number of symbols required to ensure test quality. In our approach, EVM is decomposed into its deterministic (due to static impairments: IQ mismatch, gain, AM-AM and AM-PM) and random (due to dynamic impairments: VCO phase noise, thermal noise) components. The static impairments are computed from the device under test (DUT) response to an optimized multitone test input. The dynamic impairments are computed using signal processing algorithms from the DUT test response to the same test input. The EVM of the RF system is then derived from the computed static and dynamic impairments, respectively. Experimental results show that significant reduction in test time is possible without compromising EVM test quality.

This paper proposes a new self-healing methodology for embedded RF amplifiers in RF sub-systems. The proposed methodology is based on oscillation principles in which the device-under-test (DUT) generates its test signature with the help of additional circuitry. In the proposed methodology, the self-generated test signature from the RF amplifier is analyzed by using on-chip resources for testing and controlling its calibration knobs to compensate for multi-parameter variations in the manufacturing process. Thus, the proposed methodology enables self-test and self-calibration/correction of RF amplifiers without the need for an external test stimulus, enabling true self-healing RF designs. The proposed methodology is demonstrated through simulations as well as measurements performed on an RF LNA, which were designed in a commercially-available SiGe BiCMOS process technology.

This work develops a simple, practical yet easily realizable method for low cost measurement of phase and amplitude distortions in radio frequency power amplifiers (RF PA). Amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions are two significant distortion effects in PAs at high output power levels, causing out of band interference in the transmitted signal and bit errors in the received signal. Traditional measurements of amplitude and phase distortion in RF PAs require the use of expensive vector network analyzers. In this work, we propose the use of phase-to-amplitude conversion to develop a low cost and accurate test methodology for AM-AM and AM-PM measurement using simple load board test circuitry along with software based difference generation and peak detection mechanisms. Using either simple sine wave stimulus with power sweep or a single amplitude modulated RF stimulus, both distortion effects can be measured with high accuracy for nominal devices as well as over process and voltage variations, while allowing significant reduction in test cost.

High speed signal acquisition and characterization contributes a significant amount to the total test cost of the finished product in modern high speed systems. Incoherent under-sampling allows robust and low cost signal acquisition without requiring a prior accurate knowledge of signal period. In this paper we propose a frequency estimation and signal reconstruction technique for incoherently sub-sampled periodic waveforms that is based on a time domain cost function. The method reduces the per iteration cost by a factor of log N compared to frequency domain cost functions. The proposed method estimates the period of a test signal with much fewer samples without degradation of accuracy.

Exhaustive speed testing of all the cores under extreme inter and intra-die process variations in a large chip multi processor (CMP) is expensive in terms of test time and may not guarantee full CMP functionality due to lack of coverage of timing failures induced by second-order effects such as cross talk, power/ground bounce and speed-limiting design bugs that are not "caught" by relevant combinatorial design verification algorithms. The goal of this research is to develop a methodology that allows the "safe" speed of each core in a large CMP to be determined under the assumption that some speed defects and design bugs are likely to escape conventional delay testing procedures. Accordingly, baseline speeds using conventional tests are determined for each CMP core using a comparison based speed-tuning algorithm. To prevent "blue screens" from any test escapes, relevant applications are then run on the CMP in "fail-safe/redundant" mode to "top-up" speed-defect coverage. Over a period of time, using a concurrent tuning algorithm, the true "safe speeds' of all the cores are determined in O(log(Fp)) steps, independent of the size of the array, where Fp is the number of discrete clock speeds possible. Subsequently, each core is run "independently" at its highest "safe' clock speed achieving maximum possible CMP performance.

End-of-road map CMOS (<;=10nm) technology is expected to display extreme random variability in device parameters, resulting in a very large spread in the speed of individual gates. Based on reasonable statistical estimates, virtually every large circuit in this environment can be expected to contain several extremely slow statistical outlier gates which will severely limit performance in synchronous designs. To address this challenge, gate level tuning techniques have recently been proposed [2] that can potentially speed up the slow gates to recover much of this lost performance. However, such tuning significantly increases power dissipation, and therefore must only be activated in the relative few performance limiting outlier gates. Consequently, application of such tuning techniques requires that the slow outlier gates be correctly diagnosed for proper tuning. This presents the challenging problem of diagnosing multiple delay faults in the circuit. In this paper we show how the performance tuning capability of the circuit can itself be exploited, in combination with scan delay tests, to address this problem. Our approach involves selectively tuning and speeding up subsets of suspect gates, and then uniquely identifying the slow outlier gates based on whether the tuning eliminates the slow path or not. We show that such an approach can correctly diagnose multiple slow gates in large circuits for successful performance tuning.

Process variations play a critical role in determining performance of scaled CMOS and other non-CMOS nanodevices. In this paper a power conscious post manufacture tuning technique is proposed for robust analog circuit fabrication with nanodevices in the presence of process variations. The response of the circuit to an optimized test signal is captured and using regression models, the proposed algorithm finds the best setting of tuning knobs for which the shifts in specifications from their nominal values are minimized in a power-aware manner. To demonstrate the proposed algorithm, a two stage Miller compensated operational amplifier is designed using carbon nanotube field effect transistors (CNFETs) and variability effects due to metallic CNT growth, diameter and chirality variations on the performance of the underlying circuits are studied. Suitable tuning knobs for the CNFET op-amp are identified based on the specifications to be tuned. Simulation results show that the proposed tuning algorithm enables overall yield improvement of 25.38% while minimizing power consumption of the tuned devices.

Dynamic testing of high-resolution Sigma Delta (ΔΣ) Analog-to-Digital converters (ADCs) is extremely challenging and expensive since it requires the use of spectrally pure stimulus with at least lOdB better signal-to-noise ratio (SNR) and total harmonic distortion (THD) than the ADC under test. This paper presents a low cost model parameter estimation based test and diagnosis methodology for the dynamic specifications of high-precision ΔΣ ADCs using a multi-tone test input. In the proposed test methodology, the response of a behavioral model of the ADC incorporating its key module level non idealities is matched with the response of the ADC under test by solving a nonlinear optimization problem that finds the best non-ideality parameters corresponding to the observed DUT test response. The dynamic specifications of the ADC are then calculated from the derived model parameters. The multi-tone test stimulus is designed in such a way as to maximize the accuracy with which the model non-ideality parameters can be calculated from the observed test response using a genetic test stimulus optimization algorithm. For test response analysis, the digital pulse sequence at the output of the sigma-delta modulator is made externally observable and utilized as a test access point. A key contribution is that the dynamic specifications such as ENOB, SNR, and THD of the converter as well as module level non-idealities contributing to those specifications can be simultaneously determined from the derived model parameters. The test method is fast and diagnosis is very accurate. Simulation results indicate the validity of the proposed methodology.

In wireless multimedia systems, significant power is consumed in processing image/video content This research looks specifically at the energy cost of wireless image/video transport focusing on image quality as an end metric. The quality of received image/video content depends on the effective bit error rate of the communication channel and the amount by which the image/video data is compressed prior to transmission. For a specified value of received signal quality (as determined by PSNR), the combination of the two that results in minimal RF energy consumption is first determined via an optimization procedure. Then across varying channel conditions, the baseband signal is companded and power is saved by re-biasing the RF power amplifier (PA), while maintaining the "optimal" transmission bit error rate value determined in the first step. Closed loop feedback control is used to guarantee that the received image/video quality remains within the limits set by the user. For a range of PSNR values, the average Energy/image in PA reduces by 50%, where the reference is a static system without channel quality and image quality adaptation.

Modern wireless systems are increasingly incorporating adaptability to operate at low power under varying channel conditions and to increase yield under severe process variation. Effective adaptation requires built in tuning knobs in the RF front end circuits. Due to the sensitive nature of RF circuits traditional tuning knobs affect more than one specification simultaneously. To ensure optimal adaptation it is beneficial to have carefully designed tuning knobs that allows independent control of important specifications. In this paper the design of an inductorless RF LNA is discussed whose specifications can be traded off independently/ orthogonally of each other for reduced power consumption. Two built in tuning knobs are introduced for orthogonal adaptation of Gain and linearity. The proposed LNA, designed in 0.18μ CMOS achieves a 14 dB Gain and 30 dB OIP3 control range as its power consumption goes down by 20×.

In this research, a new post-manufacture tuning approach for yield improvement of advanced RF systems is developed. The proposed method first determines module level performances from the system level response (signature) to an applied RF diagnostic test using top-down model diagnosis. Then a constrained optimizer is used to determine the best module level tuning parameter values that satisfy system level specifications (bottom-up analysis) based on the determined performances of the individual modules in a power-conscious manner. Both top-down and bottom-up analysis techniques are supported by hierarchical RF behavioral models. The health (effects of process variations) of individual modules affects the relationship between module level tuning parameters and module level performance metrics and is factored into the tuning procedure. A key benefit of the proposed approach is that only a single test application is needed. Simulation results and hardware data prove the efficiency of the proposed tuning technique.

Low cost diagnosis of RF systems has become an important problem due to increased process variability effects on the performance of RF devices and the need to ramp-up RF IC yield rapidly. In the recent past, there has been work on diagnosing RF device model parameters from random “frequency-rich” test stimulus. In this paper, we develop a novel test stimulus generation approach which produces a compact, deterministic test stimulus in such a way that the RF DUT model parameters can be computed directly from the DUT response (called the DUT signature). This is achieved through use of a non-linear solver that adjusts the DUT model parameters iteratively until the model response to the applied test matches the observed DUT test response signature. It is shown that a small set of optimized tones in the frequency domain or an optimized transient waveform in the time domain can be used as test stimulus. It is shown how the use of embedded sensors in the RF design can expedite model parameter diagnosis. The practicality and accuracy of the proposed diagnosis approach is shown through simulations and hardware measurements.

In many DSP applications (image and voice processing), several dBs of SNR loss can be tolerated without noticeable impact on application level performance. For power optimization in such applications, voltage overscaling (VOS) can be used to operate the arithmetic circuitry at or marginally below the critical circuit path delay while incurring tolerable SNR loss due to the resulting periodic errors in computation. In this paper, low cost checksum codes are used for detection and compensation of intermittent errors due to voltage overscaling in linear digital filters. In traditional coding theory, diagnosis of errors is a key problem and incurs significant computation and latency cost. In the proposed approach, low-precision shadow latches are used to identify likely sources of errors due to voltage overscaling to avoid error diagnosis. This allows accurate error compensation with distance-2 checksum codes that are normally good only for error detection but not for correction. Very precise compensation is achieved by distributing the negative of the error value evenly across only the likely erroneous states. This is called guided probabilistic compensation, as compensation is not exact when errors occur simultaneously in more than one state. A feedback controller is used for dynamic voltage overscaling (DVOS) while keeping the error rate in the system within an acceptable range. It is shown that the low cost accurate error compensation allows significant power savings with minimal degradation in system performance (SNR).

This paper presents a high-speed periodic signal acquisition technique using incoherent sub-sampling and back-end signal reconstruction algorithms. The signal reconstruction algorithms employ a frequency domain analysis for frequency estimation, and suppression of jitter-induced sampling noise. By switching the sampling rate of a digitizer, the analog frequency value of the sampled signal can be recovered. The proposed signal reconstruction uses incoherent sub-sampling to reduce hardware complexity. The results of simulation and hardware experiments indicate that the proposed signal reconstruction algorithms are able to reconstruct multi-tone high-speed periodic signals in the discrete time domain. The new signal acquisition technique simplifies signal acquisition hardware for testing and characterization of high-speed analog and digital signals.

In this paper, jitter analysis algorithms for characterizing timing jitter of multi-Gbps pseudo-random bit sequences (PRBSs) are presented. For signal acquisition, incoherent sub-sampling is employed to increase the effective sampling rate of a digitizer and to simplify its signal acquisition architecture by removing the need for timing synchronization circuits. As a substitute for these circuits, algorithms for signal clock recovery (CR) and waveform reconstruction from the acquired data are developed in this research. The algorithms utilize peak identification of the sampled signal spectrum and the sparsity of the reconstructed waveform in the frequency domain as decision making criteria for accurate signal reconstruction. The jitter value of such a reconstructed waveform is quantified with the use of a wavelet based denoising method to generate a self-reference signal against which zero-crossing times are compared to generate jitter statistics. In addition, the data dependent jitter components can be differentiated from the original jitter by analyzing zero-crossing discrepancies of the self-reference signal.

In this paper, a novel built-in tuning technique to compensate for variability induced imperfections in RF subsystems is proposed. The test stimulus is obtained from a filtered digital pattern and the RF response is down-converted using an envelope detector. The resulting signal is mapped to a digital signature, such that the Hamming Distance between the observed and the golden signature represents the degree by which the circuit specifications (Gain, IIP3, EVM, etc) differ from the ideal. A hardware driven algorithm is used to minimize this Hamming Distance to concurrently optimize (tune) multiple RF specifications. As opposed to prior research, the method does not require the use of an on-chip digital signal processor and uses minimal on-chip hardware. Results obtained on a 2.4 GHz transmitter subsystem show significant impact of tuning on device specifications.

Testing of RF circuits for gain, nonlinearity and distortion specification generally requires the use of multiple test measurements and long test times contributing to increased test cost. Prior RF test methods have suffered from significant test calibration effort (training for supervised learners) when using compact tests or from increased test time due to direct specification measurement. In this paper, a novel RF test methodology is developed that: (a) allows RF devices to be tested for amplitude and phase distortion in test time comparable to what can be achieved using supervised learning techniques while retaining the accuracy of direct specification measurement, (b) allows multiple RF specifications to be determined concurrently from a single data acquisition and (c) does not require any training for accurate test specification computation. The proposed method based on amplitude modulated RF stimulus driven RF distortion extraction is shown to give excellent results across common RF performance metrics (RMS error <;1.4%) while providing ~10× improvements in test time compared to previous methods.

The functions required of real-time systems in the future such as the ability to see or hear, understand and react to external stimulus and the environment in much the same way that humans do, will force underlying communication and computing platforms to operate across very large changes in instantaneous workload. Supporting such workload variations on resource-constrained mobile systems will require new design approaches that cut across the traditional boundaries between the processing, mixed-signal, wireless, and sensor/ actuator (physical) domains, as well as the layers of each domain, i.e. circuit, architecture, algorithm, and application. Due to components fabricated in aggressive nanoscale technologies, such cyber-physical systems must deal with the impact of manufacturing process variations and component failures as well as different environmental conditions (temperature, noise environment) while operating in the most reliable manner with respect to mission goals. An integrated approach to designing such systems that utilizes real-time, cross-domain control and adaptation to operate the system at an “optimal” point that minimizes power consumption while meeting error resilience and performance constraints across different workloads and operating environments is proposed. The core strategy relies on the design and use of tunable algorithms, tunable architectures and tunable circuits that have the capability to trade off power vs. performance. Adaptation is performed by sensing the operating environment and workload using hardware and software “sensors” and dynamically tuning the system via an optimal control law. A critical observation is that this control law depends on the health of the system when power minimization is a key objective. The core ideas are demonstrated using a video surveillance system as a test case.

In this paper, a novel methodology for continuous real time monitoring of the performance metrics of RF front end modules is proposed. The presented technique involves determination of the RF system parameters using time domain parameter estimation techniques with minimal hardware overhead. The computation of the behavioral parameters of the RF modules is performed at periodic intervals using real time signals through the use of a "parallel model" of the RF front end in the baseband DSP. During specific intervals corresponding to high signal power levels, parameter estimation of the RF front end is performed using a model in the baseband as a reference. The presented technique is used for detection/tracking of performance degradation in analog/RF front ends in real-time and does not require the use of supervised learning algorithms as with prior performance monitoring techniques. Simulation results showing accurate tracking of the distortion parameters of an RF transmitter used to demonstrate the core ideas of this research.

In this paper, a soft error resilient video encoder design is presented. The design uses the inherent architecture of modern video encoders as a basis for building a checksum based error detection mechanism. Modern video encoders use previously coded data in a video sequence as a reference to encode future data. Data prediction is efficient in terms of compression, but it enables errors to potentially affect large portions of a video sequence. The proposed Block Frame Checksum based error correction technique improves video quality by limiting error propagation. The design provides an on-line, end-to-end error detection scheme that minimizes the impact of soft-errors on video quality without reprocessing data. Additionally, scalable checksum processing provides a trade-off between power used for error detection and video quality.

Summary form only given. The demand for multi-faceted wireless applications has led to increased levels of device integration and migration of RF to CMOS technologies. However, the resulting circuits are increasingly susceptible to manufacturing process variations, coupled noise (substrate, power planes) from onchip digital signal processing circuitry, thermal fluctuations (Vt sensitivity to temperature), resulting mismatch effects and device wear-out (Vt degradation) phenomena. In the recent past, "alternative" testing methods have been used to perform parametric testing of RF transceivers.. These allow simple tests to measure complex RF specifications while at the same time allowing catastrophic failures to be detected. All (or most) of the device under test (DUT) specifications are evaluated from a single test application which may be repeated multiple times to average out noise effects.

With technology scaling, the impact of intra and inter-die process variations on the performance of mixed-signal/RF circuits has increased, making process monitoring a critical task in the overall silicon manufacturing flow. We propose a novel process-specification cause-effect monitoring scheme that allows the effects of process variations and shifts on device specifications to be monitored on a per-IC basis as opposed to existing techniques that rely only on electrical test data gathered across lots of wafers. The method relies on the use of alternate diagnostic tests under which the DUT response (alternate diagnostic signature) exhibits strong simultaneous correlation with its specifications as well as the critical process or circuit parameters with virtually zero extra test-time or test-hardware cost. Simulation results indicate that critical process parameters can be diagnosed accurately from the applied tests.

In this paper, a holistic yield recovery approach based on post manufacture tuning of RF circuits and systems under large as well as small multi-parameter process variations is developed. Marginally failing devices (small parameter deviations) are tuned using a nonlinear ¿Augmented Lagrange¿ algorithm driven optimization engine that includes test specification values and power consumption in its optimization framework. A novel built-in alternate tuning test is used to explicitly evaluate all the DUT specifications at each optimization iteration. For large parameter deviations well beyond the test specification limits of the DUT, determination of the different specification values is difficult. Such devices are tuned using a golden response tuning approach which optimizes the DUT specifications implicitly until the DUT is ¿good enough¿ to be tuned by the prior Augmented Lagrange algorithm. The proposed methodology enables yield recovery of devices not possible with earlier methods, avoids local minima and can be implemented at low cost.

In this paper, an architectural framework for post-silicon tuning of nanoscale CMOS circuits is developed. The tuning methodology is driven by a ¿tunable¿ gate design that allows the gate to be switched from a high-speed/high-power mode to a low-speed/low-power mode under digital control. A small number of ¿critical¿ logic gates are replaced with tunable gates for post-silicon power-performance tuning. In addition, supply voltage and body bias can be employed as hardware ¿tuning knobs¿ as well to deal with delay and leakage variations. After silicon is manufactured, the hardware ¿knobs¿ are programmed through the use of an implicit self-test methodology that can be exercised by the proposed self-adaptation architectural framework. It is seen that the delay yield can be improved by an average of 40% with minimal impact on area.

In the deep-submicrometer design regime, RF circuits are expected to be increasingly susceptible to process variations, and thereby suffer from significant loss of parametric yield. To address this problem, a postmanufacture self-tuning technique that aims to compensate for multiparameter variations is presented. The proposed method incorporates a ¿response feature¿ detector and ¿hardware tuning knobs,¿ designed into the RF circuit. The RF device test response to a specially crafted diagnostic test stimulus is logged via the built-in detector and embedded analog-to-digital converter. Analysis and prediction of the optimal tuning knob control values for performance compensation is performed using software running on the baseband DSP processor. As a result, the RF circuit performance can be diagnosed and tuned with minimal assistance from external test equipment. Multiple RF performance parameters can be adjusted simultaneously under tuning knob control. The proposed concepts are illustrated for an RF low-noise amplifier (LNA) design and can be applied to other RF circuits as well. A simulation case study and hardware measurements on a fabricated 1.9-GHz LNAs show significant parametric yield enhancement (up to 58%) across the critical RF performance specifications of interest.

This paper proposes a self-calibrating approach for embedded RF down-conversion mixers. In the proposed approach, the output of the RF mixer is analyzed by using on-chip resources for testing and the mixer performs self-compensation for parametric defects using tuning knobs. The tuning knobs enable the RF mixer to self-calibrate for multi-parameter variations induced due to process variability. Using this methodology, it is demonstrated that performance compensation of RF down-conversion mixers can be performed simultaneously for critical specifications such as Gain and 1-dB compression point (P1dB).

In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (ΔΣ) analog-to-digital converters (ADCs) is presented. Dynamic testing of ADCs requires an input test stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10dB better than the ADC under test. ΔΣ ADCs are inherently high resolution converters with excellent THD and SNR due to their inherent over-sampling, averaging and noise shaping properties. In the proposed test methodology, the back end digital and decimation filters of such converters are turned off and the digital pulse sequence at the output of the sigma-delta modulator is made externally observable for test purposes. It is seen that ENOB, THD and SNR of the converter can be determined with significantly increased sensitivity to device nonlinearities and noise allowing the use of less than ideal input stimulus than otherwise or significantly reduced test time. The back-end filters are then tested using traditional digital test techniques. Simulation results show the usefulness of the proposed test methodology.

In this paper, a fast RF BIST-driven post-manufacture tuning methodology for yield improvement of RF transceiver systems is presented. The core algorithms optimize multiple transceiver performance metrics concurrently using a hardware-iterated gradient search algorithm that uses diagnostic BIST data to guide the tuning of circuit and software level parameters. Intelligent ¿initial guess¿ values for the circuit and software tuning knobs at the start of the tuning process allow rapid convergence. Power consumption is given key consideration through the tuning process. Further, self-tuning is performed with little or no external tester support. The viability of the proposed scheme has been demonstrated through an experimental RF hardware prototype. Experimental results demonstrate significant yield recovery while allowing up to 10X savings in test/tuning time.

This paper proposes a novel self-healing methodology for embedded RF Amplifiers (LNAs) in RF sub-systems. The proposed methodology is based on oscillation principles in which the Device-under-Test (DUT) itself generates the output test signature with the help of additional circuitry. The self-generated test signature from the DUT is analyzed by using onchip resources for testing the LNA and controlling its calibration knobs to compensate for multi-parameter variations in the LNA manufacturing process. Thus, the proposed methodology enables self-test and self-calibration of RF circuits without the need for external test stimulus. The proposed methodology is demonstrated through simulations as well as measurements performed on a RF LNA.

CMOS technology scaling along with the resulting large variability of circuit performance has made post-silicon circuit and algorithmic level built-in test and adaptation/tuning almost a necessity for deeply scaled technologies. Currently, circuits are designed to tolerate worst-case process corners. In addition, circuits as well as demodulation/signal processing algorithms must be designed for worst case operating conditions (e.g. environmental noise). This forces designers to excessively guard band their circuits while using ldquoaggressiverdquo back-end algorithms to support the end application, resulting in unacceptable power-performance-yield tradeoffs. One way to tackle this problem is to design circuits and relevant signal processing algorithms that are cognitive of their environmental operating conditions and manufacturing process conditions and use this cognition to perform self-adaptation that conserves power while maximizing yield and reliability. Such self-adaptation involves incorporation of built-in test, diagnosis and tuning/adaptation mechanisms into the circuits and systems concerned. A key issue is that of test, diagnosis and tuning of complex circuit and system-level parameters that must be evaluated and traded off against one another during the adaptation process without access to complex external test instrumentation. This talk summarizes recent results obtained in the design of such cognitive computing and communication systems and points to directions for future work in this area.

The recent demand in wireless standards capable of providing short-range, high-speed data transfer has accelerated the growth of the Ultra-Wide Band (UWB) standard. MB-OFDM (Multi Band Orthogonal Frequency Division Multiplexing) UWB devices suffer from frequency dependent non-idealities due to extreme wideband operation (3.1 to 10.6 GHz). Further these characteristics are subjected to process variations when implemented in nanometer technologies. In this paper we propose two BIST assisted methodologies for estimation and compensation of these effects. The proposed solutions differ in hardware vs. software tradeoffs. The improvement in the linearity of the mixer over a set of process instances and the tradeoffs involved are presented to validate the proposed methodology.

Linearity testing of high resolution analog-to-digital Converters (ADCs) requires test instrumentation that has high precision digital-to-analog conversion (DAC) capability. Further, a large number of samples need to be collected for linearity testing of high resolution ADCs (18-24 bit) to guarantee test quality. In this paper a novel fast linearity testing approach is proposed for testing high resolution ADCs using a low precision DAC and a potentiometer. A polynomial fit of the transfer function of the ADC is generated using measurements made at intermediate code points. The test setup and analysis procedure makes no assumption about the linearity of the lower precision DAC or the potentiometer used to generate the ADC test stimulus. A least squares based polynomial fitting approach is used to characterize the transfer function of the ADC. The computed transfer function is then used to estimate the Integral Non-Linearity (INL) and the Differential Non-Linearity(DNL) of the system accurately. Software simulations and hardware experiments are performed to validate the proposed methodology.

Design and test of high-speed mixed-signal/RF circuits and systems is undergoing a transformation due to the effects of process variations stemming from the use of scaled CMOS technologies that result in significant yield loss. To this effect, post-manufacture tuning for yield recovery is now a necessity for many high-speed electronic circuits and systems and is typically driven by iterative test-and-tune procedures. Such procedures create new challenges for manufacturing test and built-in self-test of advanced mixed-signal/RF systems. In this paper, key test challenges are discussed and promising solutions are presented in the hope that it will be possible to design, manufacture and test ¿truly self-healing¿ systems in the near future.

There has been ongoing debate regarding the use of voltage overscaling along with error resilience techniques for ultra low power operation of scaled CMOS logic. The issue is whether to build enough design margin into future electronic systems so that errors do not impact the Quality of Service of the end application or to allow errors to occur and correct them using error tolerance mechanisms. Specific signal processing algorithms have been shown to be inherently tolerant to errors. However, large general purpose processors experience virtually zero errors under supply voltage scaling up to a certain scaling level and then exhibit “massive errors” or “complete breakdown”. The problem is made worse by the fact that low power design methodologies force devices to be sized in such a way as to make a large number of circuit paths “critical”. Under all of the above constraints, what is the best way to build low power systems of the future using deeply scaled CMOS technologies? Is the use of voltage overscaling along with error resilience techniques realistic? Can we allow errors to occur and compensate for them with high confidence? Under what conditions will design guardbanding be absolutely necessary? If we do let errors occur periodically, will customers buy the associated products and is there a marketplace for such error-resilient ICs?

Voltage overscaling for power reduction in RF systems has been limited by the need to maintain sufficient overscaling guard bands to ensure that minimum signal quality requirements of the end to end communication link are met. In this paper, we propose error control mechanisms at the symbol (probabilistic symbol remapping) and bit levels (code based correction and feedback) that allow more aggressive voltage overscaling than is possible otherwise. Error control feedback is used to continuously monitor and control the tuning knobs of the front end RF circuitry to trade off signal quality vs. power consumption. Real time image and voice data is used to demonstrate this concept. Significant power savings is achieved using the proposed scheme while maintaining minimum signal quality as required by the wireless communication link.

Amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortion are two significant effects in power amplifiers at high output power levels. Traditional measurement of amplitude and phase distortion in RF power amplifiers requires the use of expensive vector network analyzers (VNAs). This paper proposes a low cost and accurate test methodology for AM-AM and AM-PM measurement using distortion-to-amplitude conversion using simple load board test circuitry along with the use of hardware and software based difference generation and peak detection mechanisms. It is seen that both distortion effects can be measured with high accuracy while allowing significant reduction in test cost.

In this paper, a probabilistic compensation technique for minimizing the effect of transient errors effect is proposed. The focus is to develop a compensation technique for DSP applications in which exact error compensation is not necessary and end-to-end system level performance is degraded minimally as long as the impact of the ldquonoiserdquo injected into the system by the transient errors is minimized. The proposed technique, called checksum-based probabilistic compensation, uses real-number checksum codes for error detection and partial compensation. Traditional coding techniques need a code of distance three and relatively complex calculations for perfect error correction. Here, it is shown that a distance-two code can be used to perform probabilistic error compensation in linear systems with the objective of improving the signal-to-noise ratio in the presence of random transient errors. The goal is to have a technique with small power and area overhead and to perform compensation in real time with negligible latency. The proposed technique is comprehensive and can handle errors in the combinational circuitry and storage elements. Comparison against a system with no error correction shows that up to 13-dB SNR improvement is possible. The area, power, and timing overheads of the proposed technique are analyzed.

In this paper, we present an accurate linear model for estimating the minimum amount of collected charge due to an energetic particle striking a combinational circuit node that may give rise to a SET with an amplitude larger than the noise margin of the subsequent gates. This charge value will be referred to as SET critical charge (Q SET ). Our proposed model allows to calculate the Q SET of a node as a function of the size of the transistors of the gate driving the node and the fan-out gate(s), with no need for time costly electrical level simulations. This makes our approach suitable to be integrated into a design automation tool for circuit radiation hardening. The proposed model features 96% average accuracy compared to electrical level simulations performed by HSPICE. Additionally, it highlights that Q SET has a much stronger dependence on the strength of the gate driving the node, than on the node total capacitance. This property could be considered by robust design techniques in order to improve their effectiveness.

High-volume manufacturing of current generation orthogonal frequency division multiplexing (OFDM) transceivers mandates testing for error-vector-magnitude (EVM) at production testing. During EVM test, a modulated RF input signal is down-converted and demodulated to obtain the output baseband digital data and EVM is computed by processing the baseband digital data. Hence, production testing of OFDM devices would require such modulation- and demodulation-capable automated test equipment (ATE) to perform EVM test. Such capabilities significantly add up to the cost of the ATE, thereby increasing the overall cost of testing. Moreover, test time for EVM can be relatively long compared to other tests due to the need to average over a large number of data bits. In this paper, we propose a methodology for testing EVM using multi-tone signals sourced from inexpensive signal sources that generate standard constellations. Moreover, introducing null carriers in the multi-tone test stimulus enables accurate characterization of system noise with reduced number of data bits. This enables significant speedup in EVM testing. We present the theory to corroborate the proposed approach along with simulation and hardware results. The proposed test method also has the potential to significantly reduce EVM test time under production test conditions.

Polar radio architectures are attractive due to the ability to implement them using largely digital architectures. However, testing for specs such as EVM incurs significant test time due to the large numbers of symbols that need to be transmitted. In our approach, EVM is modeled as a function of the system static non-idealities (IQ mismatch, gain, IIP3 parameters) and dynamic non-idealities (VCO phase noise). Using a multi-tone test stimulus, the static and dynamic non-idealities are estimated first. The data generated is used to predict EVM using machine learning methods with high accuracy while incurring minimal test time.

In this paper, a process tunable, continuously adaptive wireless front end architecture and related adaptation algorithms are presented that allow an RF transceiver to function at minimum power irrespective of channel conditions and process variability induced performance loss in the RF front end and baseband interface. Current wireless transceiver front ends are designed for worst case channel conditions and a limited degree of post manufacture tuning is performed to compensate for process variations. It is shown how the proposed architecture can result in significant power savings over current practice without compromising system-level bit error rate. The adaptation methodology is applied to a WLAN transceiver design and hardware measurement data for an adaptive receiver is presented.

This paper presents a time-domain jitter expansion technique for high-speed digital bit sequence jitter testing. While jitter expansion has been applied to phase noise measurements of sinusoidal signals before, its applicability to random clock jitter testing and data-dependent jitter testing have not been explored. The latter problems have wide application and necessitate new analysis procedures given in this paper. Since low phase noise sinusoids can be generated relatively easily as compared to low jitter digital clocks, the proposed technique utilizes a low-frequency sine wave as a reference signal which can be fed to the device under test with less concern for reference signal noise. A special circuit called a jitter-sensor is used for jitter extraction and produces a low-speed output signal with higher jitter values that track the jitter of the high-speed digital test signal. Thus, conventional narrow-bandwidth testers are able to analyze the sensor output. This allows high resolution jitter testing for high-speed digital signals possible at low cost.

Frequency modulation is used in many important communication and wireless applications. A key defining characteristic of frequency modulated systems is the constant amplitude of the transmitted signal making it impossible to use envelope-based built-in test (BIT) techniques. In this paper, an efficient BIT technique for such transmitters using lowpass filters is proposed. The proposed BIT technique is low-cost and has minimal impact on RF transmitter performance. It can also be used to efficiently test devices such as voltage-controlled oscillators (VCOs), phase locked loops (PLL) etc through frequency discrimination. Simulation results and hardware measurements demonstrate the feasibility of the proposed approach.

In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR loss due to the resulting periodic errors in computation. In this paper, the use of checksum codes along with low precision shadow latches for compensating errors induced by voltage overscaling in digital filters is investigated. A PID controller is used for voltage overscaling while keeping the error rate in the system within acceptable range. It is shown that significant power savings can be achieved by the proposed technique.

Design of a self compensating process variation tolerant RF low noise amplifier (LNA) is described. A novel non-intrusive mixing technique is proposed which enables minimal intrusion negative feedback in RF circuits making them process variation tolerant. The proposed design technique provides 18% yield improvement over comparable conventional LNA under severe process variation.

In production testing of wireless systems, measurement of EVM (a critical spec that is directly related to bit error rate) incurs significant test time due to the large numbers of symbols that need to be transmitted for reasons of accuracy. In our approach, EVM is modeled as a function of the system static non-idealities (IQ mismatch, gain, IIP3 parameters) and dynamic non-idealities (system noise, VCO phase noise). Using a selected subset of the OFDM tones, the static parameters are calculated first. These are then used to facilitate noise estimation using a back-end constellation compensation and noise amplification procedure. The data generated is used to predict EVM using machine learning methods. Significant reduction in test time is achieved with little loss in test accuracy.

In this paper, a novel adaptive calibration technique for advanced RF front-ends is proposed in which sensors are implanted in the transmitter and the observed device test response to a special calibration test is compared against the known golden response to the same. Tuning 'knobs' which are built into the circuit are then used to minimize the error between the observed response and the golden response using an iterative tuning approach. In addition to circuit-level tuning, adaptive digital compensation techniques are employed in the baseband processor. It is shown that this results in increased transmit signal dynamic range over existing techniques and accurate loopback testing of the transceiver modules.

As channel conditions in wireless communications improve, the noise performance of the baseband DSP processor can be degraded to save power without compromising bit error rate. The degradation of baseband signal noise is achieved by degrading the noise performance (reducing the wordlength and supply voltage) of the various baseband signal processing modules in specific proportions defined by a locus, that ensures minimum overall power consumption for a given channel. In the presence of intra-die process variations, this locus is determined by the delay/leakage parameters of each baseband module. In our approach, a path oscillation test applied to each module is used to select the "best" locus of choice and an EVM driven feedback loop is used to dynamically modulate the wordlength/power consumption of each module as dictated by this locus to minimize power and modulate baseband SNR across a range of channel conditions.

Production testing of digitally modulated transceivers such as those based on orthogonal frequency division multiplexing (OFDM) has become challenging, particularly in the context of measuring specifications such as error-vector-magnitude (EVM) which require the use of precision test equipment with digital modulation capability and low noise floor. Moreover, test time is an issue due to the need to transmit and receive a large number of data bits for accurate test measurement. In this paper, a multi-tone based test method is presented for accurately measuring the EVM and noise specifications of a wireless device. We present the theory behind the proposed approach along with simulation results. The proposed test method is low-cost, and has the potential to significantly reduce EVM test time under production test conditions.

This paper presents an efficient system-level manufacturing test methodology for wireless transceiver systems. Conventional system-level testing procedures incur large test times and require the use of multiple test hardware configurations for measuring frequency and modulation-domain performance specifications, e.g., system-gain, nonlinearity, noise-figure, channel power, adjacent-channel power-ratio, error vector magnitude, modulation signal-to-noise ratio and bit error rate. The proposed test methodology addresses these problems by simplifying the test stimulus application and test response capture/analysis procedures. In addition, the number of test hardware configurations needed to measure all the performance specifications is minimized and fewer as well as shorter tests are used to determine all the test specification values of interest. Test accuracy is achieved by optimizing the test stimulus so that the observed response has strong statistical correlation with the target test specification values. Experimental results show significant testing time reduction and was validated on 1.575 GHz and 900 MHz wireless transceiver prototypes.

We propose a technique for low-cost testing of radio-frequency components integrating current signatures and alternate test methodology. The technique is suitable for non-invasive built-in test as well as low-cost automated test equipment (ATE) applications. Main features of the technique are (1) minimum loading on signal path by sampling supply current, (2) flexible test stimulus generation based on system constraints, (3) test time reduction by using a single test stimulus and data acquisition, and (4) accurate prediction of all specification values from the single excitation. Two experiments using the proposed implementation demonstrate the accuracy and efficiency of the technique on both single-balanced and double-balanced mixers built with two different technologies.

At the present time, coordinated EDA tools for RF/mixed-signal pin test do not exist. In this paper, a CAD tool for efficient production testing of high- performance RF systems using low-cost baseband ATE is presented The CAD tool consists of a custom developed genetic ATPG for spectral (Fourier spectrum) signature-based alternate (to full specification-based tests) test of RF systems and involves co-simulation of scalable behavioral-level models of the RF System-Under-Test, baseband ATE test instrumentation, loadboard resources, and DfT resources for fast test vector optimization/generation. The CAD tool also enables the evaluation of various low-cost ATE architectures on the impact of the generated tests to provide a cost-effective solution.

Defect-based RF testing is a strong candidate for providing the best solution in terms of ATE complexity and cost. However, specification-based testing is still the norm for analog/RF because of the limitations of analog fault models. Unfortunately, as the amount of functionality packed into individual devices is increased with each generation, the cost of testing larger numbers of specifications also increases. To address this, the alternate test methodology proposed in the past, which significantly cuts costs associated with specification tests by crafting a single test stimulus and mapping the response signatures into all specifications at once, can be modified for defect-based testing as well. In this work, we explore a new type of alternate test that is more fundamental than defect-based or specification-based approaches. Rather than focusing on physical defect mechanisms or the way individual specifications are measured, fault-based alternate test studies the abstractions of physical phenomena that cause specification violations; it unifies the benefits of reduced ATE complexity of defect-based approaches and the compact stimulus-signature pairs of specification-based alternate tests.

Modern wireless transceiver systems are often overdesigned to meet the requirements of low bit error rate values at high data rates under worst-case channel operating conditions (interference, noise, multi-path effects). This results in circuits being designed with ldquosufficientrdquo margins leading to lower efficiency and high power consumption. In this paper, we develop an adaptive power management strategy for RF systems that optimally trades-off power vs. performance for the RF front-end to maintain operation at or below a specified maximum bit error rate (BER) across temporally changing operating conditions. As the communication channel degrades, more power is consumed by the RF front end and vice versa. Since the maximum bit-error rate specification is not violated, minimum voice or video quality through the wireless channel is always guaranteed.

Soft errors due to alpha particles, neutrons and environmental noise are of serious concern in highly scaled CMOS circuits. This mandates the use of error/noise tolerance mechanisms in circuit design. Prior work has addressed error correction and compensation techniques for linear digital systems using checksum codes. However no low-cost checksum based technique is found in the literature for nonlinear digital signal processing systems. The problem of error detection and compensation in nonlinear systems is harder due to difficulties in encoding nonlinear operations and correcting for errors in the same. This paper presents a checksum based technique for error compensation in nonlinear digital filters using the time-freeze linearization method. The technique uses distance-two linearized checksum error detection codes for SNR improvement using probabilistic error compensation instead of deterministic error removal. It is shown that by careful checksum code design, significant filter SNR improvement can be obtained in the presence of soft errors.

It is well known that scaled CMOS technologies are increasingly susceptible to induced soft errors and environmental noise. Probabilistic checksum-based error detection and compensation has been proposed in the past for scaled DSP circuits for which a certain level of inaccuracy can be tolerated as long as system-level quality-of-service (QoS) metrics are satisfied. Although the technique has been shown to be effective in improving the SNR of digital filters, it can only handle errors that occur in the system states. However, the transient-error rate of combinational logic is increasing with technology scaling. Therefore, handling errors in the arithmetic logic circuitry of DSP systems is also essential. This is a significantly more difficult task due to the fact that a single error at the output of an adder or multiplier can propagate to more than one system state causing multiple states to be erroneous. In this paper, a unified scheme that can address probabilistic compensation for errors both in the system states and in the embedded adders and multipliers of DSP filters is developed. It is shown that by careful checksum code design, significant SNR improvements (up to 13 dB) can be obtained for linear filters in the presence of soft errors.

This paper presents a hardware jitter expansion technique to enable high-resolution jitter measurement of multi-GHz digital signals. To realize high-resolution timing analysis, the jitter is reconstructed on a low-speed signal and jitter measurements are made on this signal instead of the original high-speed signal. The reconstructed jitter on the low-speed signal occurs on a proportionately larger time-scale as opposed to the original jitter on the high-speed signal. Consequently, the jitter on the low-speed signal can be measured easily using conventional jitter measurement techniques and mapped back to its corresponding value relative to the high-speed signal. The approach allows one or two orders of magnitude smaller jitter values to be measured than standard jitter measurement techniques available today. The proposed hardware is easily implemented as a front-end to any existing jitter measurement system. Simulation data and hardware measurements are presented to prove the viability of the proposed scheme.

Recent advances in radio systems engineering have enabled the design of multiple RF front ends (transmitters and receivers), each servicing specific RF communication standards across different frequency bands in a single electronic package. While the design aspects of such radios have been rigorously researched, the test aspects are still evolving. This paper proposes a novel `alternate cross-loopback testing' scheme for a multi-hardware radio using an `optimized' multi-tone test input. In this approach, the transmitter corresponding to one RF standard is used to test receivers corresponding to the same or different communication standards and operating frequency bands. The test approach is compatible with half-duplex operation of the transceiver front-ends and works with all the signal modulation and demodulation software turned "off". Cross-loopback is achieved via a broadband mixer, a programmable VCO and attenuator in the loopback path. The multi-sine tests allow accurate prediction of all transmitter and receiver specifications

Digital predistortion is used as a compensation technique in communication systems to minimize the effect of power amplifier non-linearity while increasing its operational efficiency. Prior linearization schemes use the receiver chain to feed data to the baseband processor that adaptively adjusts the predistortion coefficients. The procedure is iterative, requires many test applications, is sensitive to receiver quality, and is not suitable for RF communication front ends in which the mixer, LNA and PA are dynamically reconfigured to adapt to changing operating conditions. In the proposed scheme, a single multi-sine diagnostic test is applied from the baseband, and the response of the transmitter is captured via a response envelope detector. A novel unified methodology for co-tuning predistortion coefficients along with the PA bias voltage based on response diagnosis is proposed, thereby, enabling the transmitter to operate at high efficiency and linearity.

Random jitter, present in the clock that is used for sampling the test input signal, is a major impediment to the signal-to-noise-ratio (SNR) measurement accuracy using the conventional dynamic testing methodology. However, most low cost testers do not provide the low-jitter clock required for SNR measurement of high-resolution and high-speed A/D converters. This paper presents a test methodology to estimate the SNR of high-performance A/D converters accurately in the presence of sampling clock jitter. The proposed approach uses the "locked-histogram" technique to gather the statistical data on the aperture uncertainty of the device-under-test. It further correlates the data obtained from the locked-histogram technique to the true SNR of the device-under-test. The proposed approach was simulated using Matlab models and validated by performing the hardware experiments. The results show an accuracy of 0.1dB in SNR estimation using the proposed test methodology

Digital and analog centric load boards have well established board check methodologies as part of their "release to production requirements", while for RF load boards this is still an open research issue. Potential faults on RF load can be caused by mechanical/electrical defects of components and sockets used on the board. Hence, we propose a novel methodology to accurately check/diagnose the RF path using only reflection measurements with suitable terminations of these paths. These reflection measurements and derived 'checker equations' are used to accurately diagnose the RF path on the load board during production test at no extra test cost. A pilot test vehicle is used to demonstrate the practical implementation and production worthiness of the proposed board check and diagnosis methodology

Smaller feature sizes and lower supply voltages make DSM devices more susceptible to soft errors generated by alpha particles and neutrons as well as other sources of environmental noise. In this scenario, soft-error/noise tolerant techniques are necessary for maintaining the SNR of critical DSP applications. This paper studies linear DSP circuits and discusses two low cost techniques for improving the SNR of DSP filters. Both techniques use a single checksum variable for error detection. This gives a distance two code that is traditionally good for error detection but not correction. In this paper, such a code is used to improve SNR rather than perfectly remove the error. The first technique, 'checksum-based probabilistic error correction', uses the value indicated by the checksum variable to probabilistically correct the error and achieves up to 5 dB improvement in the SNR value. The second technique, 'state restoration', works well when the length of burst errors is small and the error magnitude is large. A general error statistics has been defined as a random process and the distribution of SNR is compared for the two proposed techniques

Random jitter, present in the clock that is used for sampling the input signal, applied to the A/D converter results in noise that is added to the output of the device. For high-resolution A/D converters (low quantization noise), a very low-jitter clock is needed to measure accurate signal-to-noise ratio. Low jitter constraints on the clock signal increases with the test stimulus frequency. This paper implements a board-level, low-cost, phase-locked-loop (PLL) based approach to reduce the jitter present in the sampling clock provided by a low-cost tester. A small loop bandwidth PLL, a low-noise voltage controlled crystal oscillator (VCXO) and a low-cost (higher jitter) reference clock are used to synthesize a low-jitter clock. The proposed approach was simulated using Simulink and validated using hardware measurements. The results show significant improvement in RMS jitter that improves the SNR measurement of the A/D converter by 3dB

Due to aggressive technology scaling, parametric failure diagnosis of RF transceiver modules is becoming important for rapid yield ramp-up. In this paper, a low cost diagnosis approach is proposed that is amenable to built-in diagnosis of RF transceivers via diagnostic algorithms running on the transceiver DSP. The method relies on the use of a single sensor at the transmitter output that eliminates the need to make costly RF measurements. In addition, module level diagnosis is possible without the need for probing other internal RF signals. A sequence of specially crafted stimuli, are applied to the transceiver from the on-board DSP processor. The sensor and received baseband output signals are analyzed and the specifications of embedded RF modules are extracted from the test response data. The proposed approach is demonstrated using simulation and hardware measurements on a 2.45GHz transceiver. Experiment results show high diagnosis accuracy of parametric failures in embedded RF modules.

In this paper, a novel on-line error detection technique for wireless RF transmitters is proposed. Spectral features of the real time streaming data are monitored at the baseband input of the system to trigger the on-line tests whenever specific conditions on these spectral features are met. Embedded spectral sensors at specific RF nodes that generate DC output values are used to monitor the spectral response signature of the system to the real time data. The spectral features at the baseband input and the corresponding spectral signature at the RF node are jointly processed by the DSP in the system to determine the 'health' of the transmitter. The major contribution of this work is in the development of an error detection scheme that determines the health of the complex RF systems based on random streaming data as opposed to prior test methods that rely on the use of a controlled test stimulus and therefore must be run off-line

This paper summarizes an alternate test methodology that enables significant reduction in testing time and tester complexity for RF circuits without the need for low-level simulation models. Traditionally, alternate test makes use of circuit and process-level models to analyze the sensitivity of datasheet specifications to the variations in process parameters. In this paper, we demonstrate a "gray-box" approach by creating a high-level simulation model from datasheet information and simple hardware measurements. This model is used together with a customized behavioral simulator to enable efficient search of an alternate test stimulus that is optimal in terms of tester constraints, test time and specification prediction accuracy. The specific example is a third party RF front-end chip, for which 13 specifications including S-parameters, intermodulation products and noise figures are measured with both conventional and alternate methods. The results are compared in terms of testing time, tester cost and accuracy

Any error detecting or correcting code must meet specific code distance criteria to be able to detect and correct specified numbers of errors. Prior work in the area of error detection and correction in linear digital systems using real number checksum codes has shown that at least two checksums are necessary for error correction in linear digital filters and that a fair amount of computation on the two checksums must be performed before "perfect" error compensation can be achieved. In this paper, it is shown that a single checksum can be used to perform probabilistic error correction in linear digital filters with the objective of improving filter SNR in the presence of repetitive injected errors. This approach is designed to partially correct the errors. Comparison against a system with no error correction shows up to 7 dB SNR improvement using the proposed method

Recent advances in thin film micromachining techniques have spurred a new generation of smart systems incorporating microelectromechanical systems (MEMS). Extracting the mechanical properties of MEMS devices has always been a challenge in terms of test time and test cost due to difficulties associated with accurate characterization of thin films. This paper describes a novel technique for diagnosing the mechanical parameters of a cantilever-beam accelerometer using purely electrical test stimulus. The beam is stimulated with an optimized test stimulus, generated by a gradient-based search method. The response measurements made on the MEMS device are mapped to the mechanical properties of the beam using a regression-based mapping technique. Using this method, the mechanical parameters associated with the beam can be estimated within an accuracy of 5% of their actual values. In addition, the test approach is amenable to a compact built-in test solution.

"Wafer-level diagnosis" of RF systems at production test sites is difficult and incurs high investment cost. One possible solution for integrated RF transceivers is to loop-back the transmitted RF signal to the receiver input thereby enabling source and measure capabilities at lower frequencies using DC probe cards integrated to standard low cost test platforms. The design innovations in modern wireless transceivers limit the previously proposed loop-back methods for continuous wave signals for most GSM, ISM, WLAN and Bluetooth applications. To overcome these limitations, a novel loop-back DFT approach is proposed. When used in conjunction with "alternate diagnosis", transmit and receive subsystem specifications can be decoupled from the final looped-back spectral signature. The key highlight of this work is that: measurements made on commercially available TI ISM microwave transceiver TRF6903 are used to demonstrate the production worthiness of the proposed approach for RF systems

Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer combinational circuits. The tolerance estimates generated by the tool match SPICE-generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT), which uses the tolerance estimates generated by ASERTA. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation-based optimization methodology, the sizes, supply voltages, and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added capacitive loads. Experiments on ISCAS'85 benchmarks show that 79.3% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our approach has a significantly better energy-delay-reliability tradeoff compared with others.

Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose a scheme to reduce the power consumption of combinational domino logic blocks while maintaining the performance. We replace the PMOS precharge transistor with an NMOS transistor to reduce the overall power consumption of the gate at the expense of higher delay. We use a heuristic algorithm to replace the fast, high power gates on the off-critical paths with slower, low power gates while maintaining the circuit performance. Our technique reduces dynamic energy of ISCAS'85 circuits by 16.25%.

Bit error rate (BER) is a key specification that characterizes the performance of a communication receiver. In digital radio applications, running BER tests during production is highly prohibitive in terms of test cost due to the prolonged testing time required for applying RF modulated digital data-frames (each containing pseudo-random bit patterns) to the receiver and capturing the response digital bits at low baseband data-rate. Accurate and repeatable BER measurement requires the use of a large number of data-frames. In this paper, a new production testing methodology for measuring BER of wireless receivers is presented. The proposed methodology significantly reduces the time for making BER measurements by applying a sequence of AC tests. The BER value is predicted using statistical regression models that map the results of the AC tests to the expected BER value. The method also alleviates the need for using a complex BER tester (BERT). Experimental results for a 900 MHz wireless receiver are presented.

To address growing production test costs, a low-cost built-in test solution for RF circuits is proposed that is robust to Process, Supply Voltage and Temperature variations (PVT variations). The test solution consists of measuring the envelope of the output response to a twotone test stimulus. This is a relatively low frequency signal compared to the nominal frequency of the RF device under test (DUT) and can therefore be sampled using an on-chip ADC. The resulting test response waveform is analyzed using wavelet transforms. The corresponding wavelet coefficients are used to accurately predict the test specification values of the RF DUT in the presence of noise. The proposed test approach has been demonstrated for a 2.4GHz low noise amplifier designed in a 0.18um CMOS process and shows high prediction accuracy for the test specifications of the DUT in the presence of noise and PVT variations.

Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance (SET) estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate SET analysis of nm circuits (ASERTA) that can be used to estimate the SET of nm circuits consisting of millions of gates. The tolerance estimates generated by the tool match SPICE generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for SET optimization of nm circuits (SERTOPT) using the tolerance estimates generated by ASERTA. The tool finds optimal sizes, channel lengths, supply voltages and threshold voltages to be assigned to gates in a combinational circuit such that the SET is increased while meeting the timing constraints. Experiments on ISCAS'85 benchmark circuits showed that the soft-error rate of the optimized circuit decreased by as much as 47% with marginal increase in circuit delay.

Measurement of multi-tone power ratio (MTPR) on the transmitter output of a central office ADSL analog front-end device (AFE) poses stringent requirements on the linearity of the ATE digitizer. Cost of the ATE digitizer that can perform this test in a specification compliant manner is prohibitively high. In this paper, a test technique to perform TX MTPR test on a central office ADSL device using low-cost automatic test equipment (ATE) is proposed. The proposed technique is based on adding optimum dither noise to the output of the DUT, to improve the performance of the low cost ATE digitizer. The dither reduces the distortion caused by the static errors in the ATE digitizer by randomizing these nonlinear errors. Results obtained using the proposed method on ASDL AFE devices show an improvement of /spl sim/7dB in MTPR measurement with very good repeatability.

Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. In this paper, the problem of leakage power variation minimization in the presence of spatially correlated across-die process variations is addressed. It is shown that with minimal impact on delay, the placement of low-Vt gates in a layout can be performed in such a way to maximize the yield for a specified leakage power upper bound. For the obtained placement of low Vt gates, the layout can then be optimized for other important criteria such as wire length. Simulation of across-die variations for ISCAS benchmarks is performed and guidelines for distributing the low-Vt gates across the die are developed.

In this paper we present a detailed analysis on how the critical charge (Q/sub crit/) of a circuit node, usually employed to evaluate the probability of transient fault (TF) occurrence as a consequence of a particle hit, depends on transistors' sizing. We derive an analytical model allowing us to calculate a node's Q/sub crit/ given the size of the node's driving gate and fan-out gate(s), thus avoiding time costly electrical level simulations. We verified that such a model features an accuracy of the 97% with respect to electrical level simulations performed by HSPICE. Our proposed model shows that Q/sub crit/ depends much more on the strength (conductance) of the gate driving the node, than on the node total capacitance. We also evaluated the impact of increasing the conductance of the driving gate on TFs' propagation, hence on soft error susceptibility (SES). We found that such a conductance increase not only improves the TF robustness of the hardened node, but also that of the whole circuit.

Technology scaling has led to reduced noise margins and increased susceptibility of logic circuits to transient errors. In this paper, a novel methodology to increase the robustness of combinational circuits to transient errors is proposed. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation (DAV) based optimization methodology, the sizes, supply voltages and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added loads. Experiments on ISCAS'85 benchmarks show that 79.3% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our technique has a much better energy-delay-reliability trade-off compared to others.

In the nanometer design regime, analog and RF circuits are expected to be increasingly susceptible to process, noise and thermal variations. Shifting threshold voltages on the NMOS and PMOS devices of a mixer, LNA or power amplifier, for example, can affect the design specifications of such circuits (such as gain). Thermal variations can affect carrier mobilities of NMOS and PMOS devices differently, further affecting circuit performance. To solve these problems, a new self-calibration approach driven by a Specification-driven built-in self test procedure (S-BIST) is proposed. This S-BIST procedure uses alternate specification test techniques to predict the performance specifications of the circuit-under-test from the S-BIST response. The results of the S-BIST procedure are used to change the operating point of the circuit to maximally compensate the analog/RF circuit for loss of performance. The proposed S-BIST approach has been applied to a 2.4-GHz low noise amplifier and performs well in the presence of temperature and process variations.

In the recent days, ultra-wide band (UWB) has drawn significant attention as an emerging wireless standard. While the multiband (MB) orthogonal frequency division multiplexing (OFDM) PHY standards (IEEE 802.15.3a) are still being formulated, the first set of UWB devices is set to hit the consumer market by the end of 2005. For MB-OFDM UWB devices to be successful in the marketplace it is necessary for their manufacturing and test costs to be very low. To reduce the cost of production test, we propose 'alternate' tests for complex UWB transmitter specifications viz. EVM and complementary CDF (CCDF). The non-idealities present in UWB transmitters are a result of nonlinearities in DACs and ADCs, as well as the phase noise of the local oscillator (LO) used in the front-end of the transmitter. In this paper, production cost is minimized by reducing test time as well as using low-cost test equipment for performing the tests. The production tests generated for EVM and CCDF are easy to apply in a production test environment using a low-cost ATE and provides up to 10times savings in test time and 3times savings in test cost

This paper proposes a novel methodology for reducing the static linearity test time of SAR A/D converters. Due to the low data conversion rate and high resolution, the test time required measuring the linearity specifications such as INL and DNL in SAR A/D converters can be as high as 40% of the total A/D converter test time. The proposed method is based on the fact that the non-idealities in the code widths of the converter are correlated to and are dominated by the manufacturing variations in specific components used in the A/D converter design. Therefore, by measuring a subset of the total set of code widths that are directly affected by manufacturing variations in these components, all the code widths are estimated accurately. As opposed to prior work, the proposed approach does not use linear error models and describes a method which directly measures the code widths using a piecewise linear ramp designed to extract test information accurately from the relevant codes. The proposed method has been applied to a SAR A/D converter in production with achieved test time reduction of more than 75%.

As new standards are developed, designing and developing tests for the new devices conforming to the emerging standards has become a necessity. Designing new products for emerging standards needs focused effort from design engineers. In a similar manner, test is becoming a critical part of the manufacturing cycle due to escalating tester costs, as the testing requirements for every standard are different in terms of test plan development as well as the test instrumentation necessary for production test

At low frequencies, alternate testing is based on sampling the test response using an A/D converter and analyzing the digitized response in the external tester. In order to use alternate test at frequencies in the multi-GHz range, where the above is not possible, the test waveforms need to be very simple and the evaluation of the test response needs to be handled by on-chip analog test response "feature extractors". In this work, specialized functions of the output response from an alternate test are computed using built-in feature extraction sensors, which measure a complex function of the response waveform and output a DC signature. Different sensor structures are evaluated based on their performance in the presence of environmental effects and process shifts It is seen that very simple sensing circuitry can predict high quality alternate test for RF components.

The recent increase in demand within the wireless user community for short-range, very high rate data transmission (data, video) devices has spurred the growth of a new generation of 4G devices, viz. ultra-wideband (UWB). Due to its wide band of operation (3.1-10.6GHz) and non-conventional transmit/receive scheme (using short-duration, narrow baseband pulses), spectral power leakage to outside frequency bands causes interference with other wireless standards. In this paper, we focus on 'out-of-band' interference testing of UWB devices during production test. Due to stringent FCC spectrum regulations and very low power spectral density levels of the associated signals (-41.3dBm/MHz), production testing for interference is a big challenge and can incur significant test time, resulting in increased test cost. We propose a simple, low-cost test methodology for testing UWB devices. Simulation results are presented for a typical home environment. The channel model used can be easily modified and incorporated in any production test environment. Results show that using simple tests, estimates of 'out-of-band' interference can be obtained easily using the proposed test methodology.

Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are the reduced node capacitances and noise margins caused by feature size and supply voltage scaling. Static soft error optimization (such as concurrent error detection or gate resizing) can be very expensive in terms of power consumption if the circuit is not always exposed to high flux of particles. This paper proposes a scheme for dynamic control of soft error tolerance in digital circuits that has negligible power and delay overhead when the circuit is in its normal mode of operation. The key objective is to design circuits that can adapt to different radiation conditions with minimal power overhead. The soft error rate of the circuit is monitored by simple on-chip circuitry, and circuit soft error tolerance is controlled by using dynamic supply voltage and threshold voltage modulation together with variable capacitance banks.

In digital radio applications, error-vector-magnitude (EVM) is the primary specification which quantifies the performance of digital modulation implemented in silicon. Production testing of EVM incurs high cost of test instrumentation in automated test equipment (ATE). For EVM testing of wireless receivers, the ATE must include an RF transmitter having (1) the required digital modulation capability, (2) transmitter parameter configurability via test automation software and (3) higher performance and accuracy compared to the receiver-under-test. In this paper, an alternate test methodology for the EVM specification is proposed that eliminates the need for high cost RF sources with digital modulation capability. A sequence of multi-tones generated using low-cost RF sources is used as test stimuli. The EVM specification is computed (predicted) by analyzing the degradation of the test signal by the receiver modules (e.g. LNAs, mixers, filters) by means of the observed waveforms in the baseband. Simulation results are presented.

UNLABELLED: Developing a quantitative understanding of intracellular networks requires simulations and computational analyses. However, traditional differential equation modeling tools are often inadequate due to the stochasticity of intracellular reaction networks that can potentially influence the phenotypic characteristics. Unfortunately, stochastic simulations are computationally too intense for most biological systems. Herein, we have utilized the recently developed binomial tau-leap method to carry out stochastic simulations of the epidermal growth factor receptor induced mitogen activated protein kinase cascade. Results indicate that the binomial tau-leap method is computationally 100-1000 times more efficient than the exact stochastic simulation algorithm of Gillespie. Furthermore, the binomial tau-leap method avoids negative populations and accurately captures the species populations along with their fluctuations despite the large difference in their size. AVAILABILITY: http://www.dion.che.udel.edu/multiscale/Introduction.html. Fortran 90 code available for academic use by email. SUPPLEMENTARY INFORMATION: Details about the binomial tau-leap algorithm, software and a manual are available at the above website.

It is well known that wafer-probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much of the testing process into wafer-probe testing as possible to reduce the scope of assembled package testing. However, the signal drive and response observation capabilities during wafer probe testing are limited in comparison to assembled packages. In this article, it is shown that by using band-limited transient test signals, which can be supported by wafer-probe test instrumentation, significant numbers of bad ICs can be detected early during the wafer-probe test. The optimal test stimuli are determined by cooptimizing the wafer-probe and assembled package test waveforms. Overall test costs, including the cost of packaging bad ICs, are minimized and are reduced up to four times. The proposed method has been validated using hardware test data, which were obtained through measurements made on a prototype.

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.

Testing of on-chip RF and microwave circuits has always been a challenge for test engineers. Since the emergence of systems-on-a-chip (SoCs), characterization and test development for SoCs has become a significant part of the RF IC manufacturing cost. In this paper, we propose a RF built-in-test methodology using on-chip sensors. Instead of measuring the device performance metrics (not possible for embedded RF circuits), the sensor output values (low frequency or DC) are used to estimate the performance metrics of the embedded device under test (DUT). The method has high coverage of defective DUTs for low-yielding processes. An algorithm for optimal placement of sensors on internal transceiver nodes is presented and two test cases are discussed. In this paper, we use the sensor outputs to obtain an estimate of the specification values of the system and the individual modules. Using this method, test specification values can be estimated with very high accuracy.

In this paper a cost metric has been proposed, which can drive device resizing during circuit design with the objective of efficient low-cost production test of analog circuits. A test cost reduction method using dynamic and selective elimination of specification tests for fault-free circuits has also been proposed. The test elimination method exploits correlations between analog specifications. Higher correlation allows one specification to be tested (without performing measurements) against its acceptability limits by analyzing measurement data corresponding to the other correlated specification. The proposed cost metric can be imported into any typical device-resizing algorithm used in analog synthesis tools, which try to optimize circuit performance and manufacturing yield. Simulation results using op-amps show the feasibility and the effectiveness of the proposed cost metric.

An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that replace conventional specification-based testing procedures. The proposed approach is a circuit reconfiguration scheme that changes the values of one or more circuit components during application of the alternate test. The reconfiguration is designed to increase the sensitivity of the test measurement performed on the CUT to the manufacturing process variations in the components of the CUT. An algorithm REALTest for determining the optimal reconfiguration parameters and the corresponding alternate test has been presented. The validation results observed on analog circuits using the proposed approach show that the errors in the alternate test procedure can be reduced by an order of magnitude. This increased test accuracy result can improve test yield of alternate test by about 5%.

A novel algorithm for fast and accurate testing of TDMA power amplifiers in a transmitter system is presented. First, the steep cost of high frequency testers can be largely complemented by the proposed method due to its ease of implementation on low-cost testers. Secondly, TDMA power amplifiers usually have a control voltage to operate the device in various modes of operation. At each of the control voltage values, all the specifications of the power amplifier are measured to ensure the performance of each tested device. A new method is proposed to test all the specifications of these devices using the transient current response of their bias circuits to a time-varying control voltage stimulus. These results in shorter test times compared to conventional test methods. The test specification values are measured to an accuracy of less than 5% for all the specifications measured. The proposed test approach can specifically benefit production test of quad-band amplifiers (GSM850, GSM900, PCS/DCS), as a single transient current measurement can be used to compute all the specifications of the device in different modes of operation, over different operating frequencies.

Based on reliability simulation and reliability hotspot identification with simulator ARET, a concept of local design-for-reliability is proposed and a detailed redesign algorithm has been developed for CMOS digital circuits under device degradation mechanisms, such as hot-carrier and gate oxide wear-out. This algorithm improves circuit overall reliability by modifying channel length of hotspot gate and channel widths of some other gates around hotspot iteratively. By performing local redesign for reliability, circuit reliability can be significantly improved, while the originally designed overall circuit performance is still maintained.

A new approach to optical clock distribution utilizing optical waveguide interconnect technology is introduced. In this paper, we develop a new algorithm for design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. The optimization approach takes into account bending and propagation losses of optical waveguides. Less than 26.1psec in signal timing skew is obtained for a signal flight time of 614.38psec. About 15 % reduction in optical power consumption is also obtained over clock nets routed with existing (optical) methods.

Testing of on-chip RF and microwave circuits has always been a challenge to test engineers and has been more so in the recent past due to the high signal frequencies involved and the dense levels of circuit integration. In this paper, we propose to embed low-cost sensors into RF signal paths for the purpose of built-in test. The sensor characteristics are chosen in such a way that the sensor outputs, which are low frequency or DC signals, are tightly correlated with the target test specification values of the RF device-under-test. Hence, instead of testing the devices specifically for complex performance metrics (this is difficult for embedded circuits), the outputs of the sensors are used to accurately estimate the target test specification values when the device-under-test is stimulated with sinusoidal stimulus. This significantly impacts the cost of manufacturing test and allows testing to be performed using low-cost external testers. Using this method, the target test specification values can be estimated with an accuracy of /spl plusmn/5% of their actual value.

Oscillation based test (OBT) techniques in the past have focussed on detecting the existence of catastrophic and parametric faults. Recent work on predictive oscillation based test (POBT) has used OBT techniques to predict the performance parameters of the circuit under test (CUT). However, this technique cannot be used to predict the performance parameters of the CUT for process parameter variations that cause a loss of oscillation in test mode. This work presents a novel predictive quasi-oscillation based technique (PQOBT) to extend the usability of POBT over a wide range of process parameter variations with minimal test generation overhead.

This paper addresses the cost, signal integrity and I/O bandwidth problems in radio-frequency testing by proposing a feature extraction based built-in alternate test scheme. The scheme is suitable for built-in self-test of radio-frequency components embedded in a system with available digital signal processing resources, and can also be extended to implement built-in test solutions for individual RF devices that have access to a low-end digital tester. The process applies an alternate test and automatically extracts features from the component response to predict specifications like third order intercept point, 1dB compression point, noise figure, gain and power supply rejection ratio. The proposed scheme makes use of low-speed low-resolution undersampling to eliminate the need for a bulky analog-to-digital converter and the use of a noise reference for comparison makes it possible to compensate for imperfect stimulus generation. The simulation results for a 1 GHz downconversion mixer and a 900 MHz low-noise amplifier present an average of 97.3% prediction accuracy of specifications under test.

In this paper, a novel algorithm has been proposed to measure system specifications of an integrated transmitter, which capture the non-linearities of the system-under-test. The measurement of these specifications is important, as these determine the amount of "interference" created by the transmitting system in adjacent channels while transmitting data in a specific channel. By using an optimized periodic bit stream, with energy concentrated at fewer frequencies, all the specifications of interest are measured. This requires fewer measurements and hence, significantly reduced test time compared to standard test techniques. Studies show that the test time can be reduced considerably by changing the number of periods of the optimum bit-sequence without losing accuracy in measurement. The number of test measurements was reduced by a factor of two. Overall, using the proposed approach, more than an order of magnitude reduction in test time was achieved, while the different specifications were measured up to a maximum accuracy of /spl plusmn/0.2% of the actual value.

Oscillation based test (OBT) is a low-cost and vectorless test technique for analog and mixed-signal integrated circuits. Previous research with OBT has focused primarily on structural issues with an emphasis on fault detection rather than determining the conformance of the circuit under test (CUT) with its specifications, or evaluation of CUT performance. This paper presents a novel methodology for efficient interpretation of OBT results. The proposed predictive oscillation based test (POBT) methodology uses adaptive regression models to predict the performance parameters of the CUT from the oscillation measurements. Simulation results indicate that, under parametric variations, this methodology can determine CUT performance parameters, resulting in enhanced test effectiveness.

To accomplish effective IC reliability evaluation and design-for-reliability (DFR), a reliability, simulator ARET was developed at Georgia Tech. ARET simulates IC reliability at both component and system levels. It also handles the ICs with physical defects generated in fabrication by a statistical approach. ARET was verified by a series of stress tests conducted at The Boeing Company, which has shown a promising accuracy. In order to perform a practical DFR, another distinct feature - reliability hotspot identification was developed in ARET. By sensitivity analysis, it can determine the weakest components in the circuit under certain failure mechanisms, which allows a local design update to obtain an improved IC reliability. This makes DFR feasible by saving huge amount of work that needs to be performed in a complete VLSI circuit re-design for reliability.

This paper proposes an optimum methodology for assigning supply and threshold voltages to modules in a CMOS circuit such that the overall energy consumption is minimized for a given delay constraint. The modules of the circuit should have large enough gate depths such that the delay and energy penalties of the level shifters connecting them are negligible. Both static and dynamic energy are considered in the optimization. Energy savings of up to 48% have been achieved on various example circuits. The first step in the optimization finds optimum supply and threshold voltages for each module in the circuit. If the circuit has a large number of modules, this step might yield a correspondingly large number of different supply and threshold voltages for minimum energy consumption. Since having a large number of different supply and threshold voltages on an IC is not feasible in current technologies, an additional step clusters the multiple voltages obtained from the first step into a fixed number of supply and threshold voltages (for example, 2 different supply voltages and 2 different threshold voltages). In addition to the application of this method to circuit optimization, it can also be applied to a wide range of problems with delay constraints, such as software tasks running on a dynamically variable V/sub DD/ and V/sub th/ processor.

In this paper, we propose an efficient approach to minimize total power (switching, short-circuit, and leakage power) without performance loss for ultra-low power CMOS circuits in nanometer technologies. We present a framework for combining supply/threshold voltage scaling, gate sizing, and interconnect scaling techniques for power optimization and propose an efficient heuristic algorithm which ensures that the total slack budget is maximal and the total power is minimal in the presence of back end (post-layout-based) UDSM effects. We have tested the proposed algorithms on a set of benchmark circuits and some building blocks of a synthesizable ARM core. The experimental results show that our polynomial-time solvable strategy delivers over an order of magnitude savings in total power without compromising performance.

In the past, it has been diflcult to perform test generation for complex RF subsystems due to the cost of repeated system level simulation necessary for running a test generation algorithm. In this paper, a new test generation method for RF sub-systems driven by behavioral models is presented. The test generator produces an optimized multi-tone test stimulus (alternate test) from which the subsystem test specifcations can be simultaneously computed. The test generation algorithm attempts to maximize the accuracy with which all the system test spec$cations can be determined from knowledge of the different ways in which perturbations of the behavioral model parameters affect the test specifications. Pass/fil test decisions are made using the specification values computed from the observed test response (single test). Simulation results using the proposed test approach show accurate tracking of multiple system speci$ca fions, such as gain and IIP3 for the receive channel of an RF transceiver, with an error within fl dB.

It is well known that wafer probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much as the testing process into wafer-probe lest as possible while limiting the scope of assembled package test. However, the signal drive and response observation capabilities during wafer probe lest are limited in comparison to assembled package test. In this paper, it is shown that by marginally increasing the capabilities of wafer probe lest equipment to include low-speed transient signals, significant numbers of bad ICs can be detected early during wafer probe lest. The optimal test stimulus is determined by co-optimizing the wafer-probe and assembled package test waveforms. Overall, test costs, including the cost of packaging bad ICs are minimized.

This paper presents a novel concurrent fault simulation algorithm for nonlinear analog circuits. Between successive time steps in transient fault simulation, all faulty circuits in the fault list are simulated before the simulator proceeds to the next step. Four primary techniques, including fault grouping, fault ordering, state prediction, and reduced-order fault matrix computation, are proposed to significantly reduce analog fault simulation complexity by making use of the similarities between the faulty and fault-free circuits. The method has been implemented in a dc and transient fault simulator called CONCERT2, which is the first ever for nonlinear analog circuits. Up to two orders of magnitude speedup is obtained for complete transient fault simulation, without loss of accuracy in fault detection. It is shown that the methodology of CONCERT2 can significantly speed up the process of analog test stimulus generation.

Production test costs for today's RF circuits are rapidly escalating. Two factors are responsible for this cost escalation: (a) the high cost of RF ATEs and (b) long test times required by elaborate performance tests. In this paper, we propose a framework for low-cost signature test of RF circuits using modulation of a baseband test signal and subsequent demodulation of the DUT response. The demodulated response of the DUT is used as a "signature" from which all the performance specifications are predicted. The applied test signal is optimized in such a way that the error between the measured DUT performances and the predicted DUT performances is minimized. The proposed low-cost solution can be easily built into a load board that can be interfaced to an inexpensive tester.

A wiring model for system-on-chips utilizing flexible free space optical interconnects is introduced In this paper, we develop a CAD tool for physical placement of modules in system-on-chips manufactured using the optical interconnect technology. The tool also determines which of the interconnect are routed electrically and which are routed optically without exceeding the routing capacity of the optical interconnect while minimizing electrical wire length. About 50% reduction in largest delay of electrical wires is obtained through the use of optical interconnect (Performance improvement by a factor of 2).

This paper describes an efficient hierarchical design and optimization approach for ultra-low power CMOS logic circuits. We introduce the Hierarchical Activity-Aware Time Slack Distribution (HA2TSD) algorithm, which distributes the surplus time slack into the most power-hungry modules hierarchically. HA2TSD ensures that the total slack budget is maximal and the total power is near-minimal. Based on these time slacks, we have optimized technology parameters (supply voltage, threshold voltage, and device width) through a gate-level power optimizer and have tested the algorithm on a set of benchmark example circuits and building blocks of a synthesizable ARM core. The experimental results show that our strategy delivers over an order of magnitude savings in total (static and dynamic) power and reduces the optimization run-time significantly.

Parasitic capacitance in test hardware can affect the performance of a test and lead to poor fault coverage and/or yield loss. In an ATE setup, characterizing the stray capacitance using external instruments is difficult for practical reasons. In this paper, we present a single probe technique that uses available tester resources to measure stray capacitance of test hardware with high accuracy and precision. The proposed method uses a time measurement sub-system and a current source of the ATE for measuring stray capacitance from their charging and discharging characteristics. This capacitance measurement technique is also used to detect and diagnose faults in different tester hardware components. Measurement results and case studies on the application of this technique are presented.

In this paper, a fast transient testing methodology for predicting the performance parameters of analog circuits is presented. A transient test signal is applied to the circuit under (cut) test and the transient response of the circuit is sampled and analyzed to predict the circuit's performance parameters. An algorithm for generating the optimum transient test signal is presented. The methodology is demonstrated in a production environment using a low-power opamp. Result from production test data showed: 1) a ten times speedup in production testing; 2) accurate prediction of the performance parameters; and 3) a simpler test configuration.

Measurement of Parametric specifications like delay, power, gain, etc., is difficult, expensive and require specialized test instrumentation, as they are essentially analog in nature. Due to these problems, alternate tests are used to implicitly verify parametric specifications. For most nontrivial circuits, alternate test generation is a time-consuming and complex task. In this paper, we utilize a novel technique for fast exploration of the specification space to determine redundancy in specification tests prior to alternate test generation. If significant redundancies exist, a low dimensional embedding is determined to provide a target for the classification method operating on the alternate test measurements. The proposed method uses the same data that is generated by conventional tests, hence requiring minimal additional effort in data collection and can also be used on high dimensional data with complex nonlinear structure.

In this paper we present a new low-cost, digital compatible and efficient built-in test scheme for analog circuits. Using the proposed test methodology both catastrophic and parametric failures can be detected with very little on-chip hardware. The test methodology uses a vernier technique to digitize the response of the circuit-under-test (CUT) with the help of a voltage comparator and simple reference waveform generator circuit. The digitized response is scanned out of the system using digital scan and analyzed externally for precise reconstruction of the response waveform. The specifications of the embedded analog circuit can be predicted accurately from the reconstructed waveform for making pass/fail decisions. Simulation results are presented.

The problem of test generation for analog circuits is made complicated by the fact that most test generation algorithms use repeated circuit simulation to derive the optimal test stimulus and this is very expensive in terms of computer time. In this paper, we introduce the notion that during test generation, the circuit models need capture only those aspects of the input-output behavior of each circuit module that relate to the kinds of waveforms that the circuit and its constituent modules will see during the testing process. This is usually a small subset of the total space of waveforms that can be applied to the circuit-under-test during regular operation Hence, during repeated simulation for test generation, much simpler circuit models can be used to significantly speed up the test generation process These simple models, referred to as test transfer function models do not compromise test quality or fault coverage Preliminary results for small-signal AC testing of analog circuits show the potential of the proposed approach.

With the increasing complexity of manufacturing processes and the shrinking of device geometries, the performance metrics of integrated circuits (ICs) are becoming increasingly sensitive to random fluctuations in the manufacturing process. We propose a diagnosis methodology that can be used to infer the cause(s) of variations in performance of analog ICs. The methodology consists of (a) a device parameter computation technique which is used to compute the device parameters of an IC from measurements made on it and (b) a cause-effect analysis module that is used to compute the cause of the variation in performance metrics of a given set of ICs. Simulation results to demonstrate the effectiveness of the technique are presented.

In this paper, we propose a new technique for jitter measurement that can be implemented using commercially available, off-the-shelf components. The technique implements a high-resolution, high-speed, phase detector using a high-speed Analog-to-Digital Converter (ADC). The technique is shown to have high resolution and low test time compared to currently available techniques. Experimental results to demonstrate the effectiveness of the technique are presented.

A hierarchical diagnosis algorithm is presented for testing identical units in a system. As all units are similar, it is essential that the test process be parallelized to enable test of multiple units for the cost of testing one unit. With this objective in mind, we propose a novel test architecture consisting of a hierarchy of testers in a system to test all the units simultaneously. In this approach, special test chips are placed at strategic locations in a system to compute a "golden response" by analyzing the responses of all units. The responses are propagated up the hierarchy of testers. At each level, the testers analyze the data and pass golden response computation data to testers at higher level. The tester at the top of the hierarchy computes the golden response and the test result is percolated down to the testers at the lowest level that identify faulty and fault-free units. Using this diagnosis approach, almost all units are correctly diagnosed, even when yields are as low as 40 percent. The hardware architecture of all test chips is identical and simple. This approach can be used for testing massively parallel multiprocessor systems, MCMs fabricated on a large area panel, and integrated circuits on silicon wafers.

A boundary scan-based algorithm is presented for testing iterative arrays of identical units such as integrated circuits on silicon wafers, MCMs fabricated on a large area panel, and multiprocessor systems. As all the units are similar, it is critical that the test process be parallelized in order that multiple units may be tested for the cost of testing one unit. With this objective in mind, we propose a parallel and pipelined boundary scan standard-based scheme for testing all units simultaneously. In this scheme, the test vectors and the corresponding correct-response vectors are both scanned into the scan chain of the units in an interleaved fashion, optimally utilizing the resources of every chain to test all units. The comparison of the expected versus the observed response of a unit is performed locally at each unit. Our algorithm provides an order of magnitude speed-up in test time over conventional boundary scan based testing schemes. Further, as the number of chains increases, the test time tends asymptotically toward the optimal. The complete design of the test architecture is also presented.

A new methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. The paper illustrates a structural representation, called the suspect circuit, of all the possible path delay faults in a faulty circuit. This representation has been used to design efficient algorithms that enable us to manipulate the suspect faults without having to enumerate them explicitly. Procedures for removing fault-free paths from the list of suspect faults have been implemented to improve the diagnostic resolution. Moreover, efficient data structures are used to complement the procedures and reduce the memory footprint of the algorithms. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.

A novel scheme of synthesizing nonlinear feedback shift register structures that can be superimposed on the boundary of the component of a system under test to generate interconnect switching activities that resemble real life interconnect switching profiles is proposed. The goal is to perform at-speed interconnect test while simultaneously capturing the dynamic switching effects such as crosstalk and ground bounce, as accurately as possible during interconnect built-in self-test. A library of nonlinear feedback shift register structures called precharacterized test pattern generators (P-TPGs) is constructed. Components of P-TPGs can be modeled using Markov chain and can be interconnected together in specific ways to recreate the switching activity profile of the interconnections being tested. The unique advantage of this scheme is that there is no simulation overhead since P-TPG components are precharacterized by solving Markov equations analytically. An integrated genetic algorithm-based search and optimization technique for finding the best P-TPG component among various possible implementations and matching its activity profiles with those of the interconnections under test has been designed and implemented synthesis for testability allows generation of the worst case interconnect switching activities. Experimental results confirm the validity of our approach.

Test generation techniques to isolate failures to different parts of an analog circuit, have relied on a list of failure modes being available for the circuit being tested. This may be difficult to obtain for general analog circuits. In this paper we propose a new methodology for isolation of parametric failures in analog circuits that (a) does not require a fully specified fault list, (b) is able to work with high-level behavioral descriptions of the various sub-modules of the CUT (c) is able to isolate faults caused by multiple parameter variations in the CUT and (d) is robust in the presence of measurement noise and manufacturing tolerances of analog components. Experimental results to demonstrate the effectiveness of the proposed technique are presented.

In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-under-test, the proposed test generator computes the optimal transient test stimuli in order to detect and isolate a given set of faults. It also computes the optimal set of test nodes to probe at, and the time instants to make measurements. The test generation program accommodates the effects introduced by component tolerances and measurement inaccuracy, and can be tailored to fit the signal generation capabilities of a hardware tester. Experimental results show that the proposed technique can be applied to generate transient tests for both linear and non-linear analog circuits of moderate complexity in reasonably less CPU time. This will significantly impact the test development costs for an analog circuit and will decrease the time-to-market of a product. Finally, the short duration and the easy-to-apply feature of the test stimuli will lead to significant reduction in production test costs.

Fast analog fault simulation is critical in test development and fault diagnosis for analog and mixed-signal circuits. It has been demonstrated that concurrent fault simulation methods can greatly reduce the computational complexity of analog fault simulation by sharing intermediate simulation results between different faults. In this paper we present an algorithm for dynamic fault grouping for transient fault simulation of nonlinear analog circuits. The goal of fault grouping in general is to minimize the total fault simulation running time for all faulty circuits while satisfying the simulation accuracy constraints. Fault grouping allows subset of faults with similar transient response characteristics to be simulated concurrently for a given test stimulus. Time step increments for each fault group are adaptively selected to limit simulation error while maximizing simulation concurrency. Results of simulation performance and statistics on test circuits are presented.

As Analog to Digital Converters continue to improve in resolution, their linearity testing has become increasingly challenging in terms of test accuracy and test time. In this paper we present a technique for estimation the linearity metrics of an ADC that is optimal in terms of expected r.m.s error in INL/DNL estimates, for a given test time. Experimental results measured on an ADC from industry to validate the effectiveness of the technique are presented.

A new methodology is developed in this paper for identifying possible path delay faults through at-speed testing of sequential non-scan circuits. In the past, different techniques have been proposed for diagnosing delay faults in sequential circuits through variable clock control techniques. These techniques are, however not readily applicable to commercial high-performance ICs. We propose new techniques based on critical-path tracing which can be used to locate slow paths in sequential circuits. Strategies have been developed to improve the diagnostic resolution, which involve deducing internal state values from the observed circuit outputs and the detection of fault-free circuit paths. Results of experiments on the ISCAS89 sequential benchmark suite are finally discussed.

ATPG approaches for analog circuits in the past have targeted the testing of catastrophic and parametric faults. It has been shown recently that analog circuit specifications can be predicted from the transient response of the circuit under test. In this paper, we present a new ATPG algorithm for synthesizing a test stimulus that enables accurate prediction of circuit specifications from its response to the test stimulus. Use of simple linear models for ATPG and more complex nonlinear models for specification prediction results in a test generation procedure that is both accurate and simulation efficient. Due to the incorporation of measurement noise during test optimization, robust specification prediction is possible.

In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space representation and adjoint network method is also presented. This fault simulation algorithm is used for generating transient test for linear analog circuits. For nonlinear circuits, an existing circuit simulator is used for test generation. The generated tests are evaluated and found to give low misclassification rates for a large class of analog circuits.

We propose a new Simulation-After-Test (SAT) methodology for accurate diagnosis of circuit parameters in large analog circuits. Our methodology is based on constructing a non-linear regression model using prior circuit simulation, which relates a set of measurements to the circuit's internal parameters. First, we give algorithms to select measurements that give all the diagnostic information about the Circuit-Under-Test (CUT). From these selected measurements, we solve for the internal parameters of the circuit using iterative numerical techniques. The methodology has been applied to several mixed-signal test benchmark circuits and has applications in process debugging for mixed-signal integrated circuits (ICs) as well troubleshooting and repair of board level systems.

In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated to sequentially synthesize the test stimulus for the entire duration of test. We use a novel measurement procedure to resolve ambiguities in the present measurement sample by using class association information from the previous samples. This sequential formulation of test generation problem enables fault dropping and greatly reduces simulation and optimization effort. Additionally, this method is immune to noise and tests can be easily calibrated for use in hardware testers.

We propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is formulated as a solution to a multi-point boundary value problem (BVP), with constraints on the output state and the input. This error constraint minimizes large spurious deviations in the input signal and the convergence problems that arise if multiple solutions exist or if the desired signal does not exist in the feasible signal space. As an additional attractive advantage, this formulation preserves the core iteration structure of a SPICE-like simulator without modifications, greatly easing implementation.

A novel methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. We seek to provide an improved understanding of the methods introduced by Y.-C. Hsu and S.K. Gupta (1998), with the goal of devising efficient representations and algorithms for the diagnosis of path delay faults. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.

In this paper, we propose a novel concurrent error detection scheme for linear digital variable systems that significantly reduces the hardware overhead of the detection circuitry. A new theory of extrapolated checksums has been developed. A novel test point selection algorithm has been proposed to select the minimal set of test points without compromising fault coverage. Techniques for selecting code vectors (to compute checksums) and designing error detection circuitry have been discussed. Experimental results indicate significant hardware reduction in the error detection circuitry.

Dynamic transient tests can give better parametric and catastrophic fault coverage than both static DC and frequency domain AC tests in minimum test time. However determination of optimum transient tests is a complex search problem. Previous researchers have used accurate but computationally expensive fault simulation to guide the search for the optimum transient tests. In this paper we propose to use partial numerical simulation to guide the search for the optimum input test stimulus. The proposed method dynamically adjusts the number of Newton Raphson iterations and transient simulation time steps to perform fast test generation without sacrificing the test quality (fault coverage). This heuristic relies on the observation that although partial numerical circuit simulation may be inaccurate for determining the exact faulty circuit response to an applied test stimulus, it can determine very well how one test stimulus performs relative to another in detecting a fault. Simulation studies show that test generation using partial numerical simulation can generate high quality tests much faster compared to test generation methods based on accurate simulation without compromising test quality.

In this paper, we propose an efficient test generation scheme for analog circuits consisting of embedded modules. The proposed scheme simplifies the test generation effort by incrementally generating tests for the individual embedded modules rather than for the full circuit. At each step of the test generation process, the test waveform is incrementally optimized. As input nodes to an embedded module are not directly accessible, the test optimization considers only those waveforms that can be justified from an embedded module input to a primary input of the circuit-under-test using a signal backtrace procedure. The "best" selected test is then evaluated at the full circuit level for controllability of the test stimulus and observability of the test results. In this manner, repeated evaluation of the full circuit over the search space of all test stimuli is not necessary and the complexity of test search can be reduced.

In this paper, we investigate the problem of electrical testing of multichip modules (MCM's) substrate interconnections prior to chip assembly. Recently, single-probe test techniques for MCM substrate interconnections have been proposed that provide fault coverage comparable to double-probe test techniques. This work has two objectives. First, we assess the advantage of single-probe test techniques over double-probe techniques where overall test time is concerned. Second, we develop efficient heuristics to optimize the total distance traveled by a single test probe on an MCM substrate and thereby reduce the substrate testing time. We provide tight bounds on both single- and double-probe testing times. For substrates with two to three terminal pads in each of n nets, the expected travel time for a single probe is shorter by a factor of order n/sup 1/4 /. Experiments on benchmark MCM netlists with real probe traversal speeds confirm that single-probe testing has an increasing advantage over double-probe testing, as the number of nets increases. For an MCM substrate of 800 nets, the projected test time is faster by a factor of 2.5. A practical algorithm for finding efficient traversal routes is presented. It is based on heuristic procedures of tour construction and local improvement for solving a variation of the traveling salesman problem. Experiments show that up to 40% reduction in probe traversal time can be obtained with our algorithm.

This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits.Three prima~techniques in CONCERT including fault ordering, state prediction, and rednced-order fault matrti computation, greatly simplifi fault sittudation by making use of the residual similarities bem'een the faul~andfault$ree circuits.Be~een successive time steps, all circuits in the fanlt list are simulated concurrently before the simulator proceeds to the nert titne step.CONCERT also generates accurate fault co~'erage statistics that are tied to the circuit specifications.Up to nt,o orders of magnitudes speedup are obtained for cotnplete fault simulation, )t'ithout any loss of accuracy.More speedup is achieved by COiVCERT for evaluating the fault coverase of a test, using fault ordering and fault dropping technique. AchowledgmentiThe author would like to tha~Ram&rishna Voor4aranam and Pramodchandran N Variyam for help and valuable discussions.

The issue of performance testing of MCM interconnections is becoming very important due to the fact that hitherto second order effects such as ground bounce, crosstalk and switching noise are playing dominant roles in current design methods due to shrinking dimensions, lower supply voltages, higher clock speeds and higher density packaging. We propose a novel scheme for synthesizing nonlinear feedback shift register structures that can be superimposed on the boundary scan cells of ICs to generate MCM interconnect switching activities that resemble real life interconnect switching profiles. The goal is to perform at speed MCM interconnect test while simultaneously capturing the dynamic switching effects referred to earlier as accurately as possible during interconnect BIST. A library of nonlinear feedback shift register structures called Precharacterized Test Pattern Generators (P-TPG) is constructed. Components of P-TPGs are interconnected together in specific ways to recreate the switching activity profile of the interconnections being tested. An optimization algorithm for matching the P-TPG component activity profiles with those of the interconnections under test has been designed, and implemented experimental results confirm the validity of our approach.

In this paper, we propose a novel test technique for fault detection and automated fault diagnosis using pole/zero analysis of embedded integrated passive. For pole/zero analysis, an ensemble of circuits obtained by perturbing the circuit under test parameters using their known statistical distributions is generated. The poles and zeros of every circuit in this ensemble are extracted. From knowledge of the passive circuit specifications, pass and fail regions for the critical poles and zeros are computed in the real-imaginary plane. The proposed test technique uses a region-matching algorithm to detect faults and perform automated diagnosis of catastrophic and parametric faults using frequency domain 2-port measurements.

This paper describes a new high throughput test methodology for a new multi-chip module (MCM) substrate. This is based on a new MCM substrate technology which contains interconnects, embedded passive devices, and mixed-signal circuits, currently being developed by the Packaging Research Center at Georgia Tech. The resulting MCM modules are called SLIM (single layer integrated module). In this paper a best methodology for SLIM modules is discussed.

A general description of an enhanced scheme for designing completely self-testable MCMs is given. It allows performance testing and diagnosis of MCM interconnections for dynamic effects. This scheme is based on embedding of cascadable test pattern generators and reconfigurable signature analyzers into the design of MCM dies. A theory of partitioning of linear registers is applied to devise a two phase distributed diagnosis strategy The design of a novel MISR reconfiguration scheme that enables high diagnosis resolution, is presented. Simulation results obtained confirm the effectiveness of our BIST technique.

The use of alternate tests in addition to specification-based measurements is achieving more recognition in industry due to the higher coverage that they provide. The fault and yield coverages of these tests depend on how the pass/fail test decision is made. In this paper we address the critical issue of accurate test threshold determination for these alternate tests. We propose to post-process the given set of sensitive and linearly independent measurements to synthesize a new set of measurements based on which the pass/fail decision is made. A novel methodology for post processing the measurement results called measurement synthesis is presented. Simulation results show that test effectiveness can be greatly enhanced by measurement synthesis.

In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in a hierarchical manner. The effects of parameter variations in one level of design hierarchy on those of the next are mapped through linear and piecewise linear sensitivity functions. The models allow computation of the statistical distributions of the circuit parameters and their correlations. This data is used to determine the critical circuit specifications that must be measured and those that may be eliminated from the testing process.

While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. The primary difficulty in analyzing signatures for analog signals is that the latter are imprecise in nature. Therefore, deterministic signature analysis schemes, such as those based on finite-field arithmetic using linear feedback shift registers, are unsuitable for analog circuits. In this paper, a novel signature analysis scheme for analog and mixed signal circuits is proposed. The signatures possess the interesting property that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold; the larger the effects of the failure, the larger the difference between the generated signature and the expected signature. The probabilities of aliasing and false rejection are also derived. Results for an example filter circuit are presented.

We demonstrate a new approach minimizing the total ofthe static and the dynamic power dissipation components in aCMOS logic network required to operate at a specified clockfrequency using joint optimization of both device and circuitdesigns for a specific logic schematic and activity profile.We present a new approach to designing ultra low-powerCMOS logic circuits by joint optimization of supply voltage,threshold voltage and device widths for a specified speedconstraints.The static (leakage) and dynamic (switching)energy components are considered and an efficient heuristicis developed that delivers over an order of magnitude savingsin power over conventional optimization methods.

The problem of testing analog components continues to be the bottleneck in reducing the time-to-market of mixed-signal ICs. We present a test generation algorithm for implicit functional testing of linear analog circuits using transient response sampling. Each specification of the circuit under test (CUT) imposes bounds on individual parametric deviations under the single fault assumption. These bounds are mapped on to "acceptable" ranges of measurements of the transient response of the CUT at various sample points using time domain sensitivity calculations. Any circuit that "passes" the applied test is also guaranteed to meet its specifications. The simplicity of the test waveform, reduced test generation time and test time show that this testing method is a good alternative to existing testing schemes.

In this paper we discuss the capabilities of the MiST PROFIT (Mixed Signal Test Program for Fault Insertion and Testing) software for hierarchical fault modeling, tolerance modeling, fault clustering and fault diagnosis of complex mixed-signal systems. The software is designed to exploit the relationships between high level system specifications and module-level faults in complex and nonlinear mixed signal systems. Hierarchical simulation based methods are used to capture fault effects at different levels of circuit abstraction. The key features of our approach are: (a) the ability to compute tolerance effects from nonlinear behavioral models at different levels of circuit design hierarchy accurately using low-cost simulation based methods, (b) the ability to perform compaction of fault effects while transferring fault effects from the leaf cells to the highest level behavioral models, (c) the ability to capture parametric (soft) failure effects over the entire anticipated range of faulty parameter values and (d) the ability to construct fault dictionaries given a set of least replaceable units to diagnose.

In this paper an efficient low-cost built-in self test (BIST) scheme is proposed for analog circuits. The key idea is to use rectangular pulses of random widths obtained directly from a digital linear feedback shift register to perform transient testing of the circuit under test. A small amount of synchronization and comparison circuitry is necessary to perform the BIST. A methodology for designing the BIST hardware is described and results are discussed. The method is seen to be both efficient and low cost.

Concurrent error detection in digital circuits is very important in applications where error in processed data can have catastrophic effects. Typically, error detection is performed by a small amount of additional hardware called the checking circuit. In the past, researchers have developed techniques for concurrent error detection in linear digital state variable circuits. In this paper, we investigate concurrent error detection techniques for nonlinear digital circuits that compute polynomial functions of multiple variables. Such circuits have widespread use in the design of various classes of nonlinear digital filters. The proposed error detection schemes are possible due to the use of a new linearization method called time-freeze linearization. In this method, a nonlinear circuit is modeled as a linear circuit for each individual time frame corresponding to the time taken to process a given set of input data. The defining parameters of this linear model change from one time frame to another but are regarded as fixed or frozen in any given time frame. This allows the use of real number checksum codes for fault detection. As opposed to duplicating the entire nonlinear part of the circuit, our approach allows us to use the nonlinear functions to drive the check circuitry, while achieving full fault coverage at low hardware cost.

An algorithm for finding the optimal traversal route of a single probe to test MCM interconnects is presented. The goal of this work is to optimize the total distance traveled by a single test probe on an MCM substrate and thereby reduce the substrate testing time. It is assumed that only one terminal pad of each interconnection net is to be probed. Our algorithm is based on tour construction and improvement with arbitrary insertion for solving a complex variation of the traveling salesman problem. Improved insertion and shuffling techniques guarantee the step by step optimization of the total traversal cost. The validity of the algorithm has been confirmed with experiments and shows that up to 50% reduction in probe traversal time can be obtained with our technique.

One of the key factors that has prevented multi-chip modules (MCMs) from gaining mass acceptance in the electronics industry is their high cost. Often contributing to as much as 40% of this cost is the cost of testing the MCMs after they are manufactured. In this paper, we address the problem of testing MCMs fabricated on large area substrates, analogous to the way ICs are manufactured on silicon wafers (this reduces manufacturing cost). Our objective is to reduce the cost of testing MCMs by parallelizing the test process. In this paper we propose a novel relay propagation scheme in which the test stimuli and their correct responses are scanned in an interleaved and pipelined manner into the MCMs. Comparison of the observed and the correct response for each test vector is performed locally at each MCM. It is shown that our scheme results in drastic speedup over conventional boundary scan based testing. We also show that the test time using our testing methodology asymptotically approaches the optimal with the use of larger numbers of test chains.

In this paper we propose to use an output signal waveform analysis method called signal waveform integration for detection of stuck-at failures in combinational circuits. Non-robust tests are applied at-speed or faster to achieve high fault coverage, low test application time and detectability of redundant faults using directed random test generation techniques.

Consistent with industry needs for low-cost MCM substrate test methods, we have earlier developed a single-probe technique for detecting near-opens and near-shorts in substrate interconnects. In this paper we show how a fault-dictionary can be used to accurately determine defect location, size, etc. Such information may be used to perform repair of MCM substrates.

This paper describes a novel and low-cost technique for detecting process-related interconnect faults in MCMs. This method is an alternative to existing test methods such as TDR, TDT electron beam, and capacitance techniques which are either expensive in terms of test equipment, are cumbersome due to the requirement of multiple probes, or provide poor fault coverage. The proposed technique applies a stimulus through a tuned load and a single probe at one end of the interconnect. By measuring the attenuation of the test stimulus due to pole movement relative to known attenuation measurements, interconnect faults such as near-opens, near-shorts, opens, and shorts can be detected. The total test time is small and the hardware cost of test equipment is low. Extensive simulations have been performed to show the validity of the method.

This paper addresses the issue of testing MCMs on large-area substrates. The cost of testing each MCM may be as high as 40% of the total manufacturing cost. It is critical that the test process be parallelized in order that multiple MCMs may be tested for the cost of testing one MCM. With this objective in mind, we propose a distributed probabilistic diagnosis algorithm for MCMs on large-area substrates. Our algorithm performs better than the existing diagnosis algorithms and can correctly identify almost all MCMs even when the yield is very low (35%). Further it provides upto an order of magnitude reduction in test application time as opposed to serial MCM probe test.

This paper presents an efficient dc MOSFET model for accurate simulation of analog circuits. A new approach to model channel length modulation is presented. An empirical expression for channel length modulation is derived from measurements. This is used to model the observed behavior of g/sub D/ with gate, drain, and substrate bias. Some of the models commonly used for circuit simulation do not predict the effects of gate and substrate bias adequately. A new smoothing function is used to unify the linear and saturation regions in a single expression. Continuity of transconductance is maintained between the weak and strong inversion regions. Model efficiency is maintained by avoiding the use of transcendental functions in the smoothing techniques. We demonstrate>

While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. In this paper, a novel signature analysis scheme for analog and mixed-signal circuits is proposed. The signatures possess the interesting properly that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold.>

Fault diagnosis in digital signal processing (DSP) circuits is very important for debugging circuit prototypes and chips and for identifying manufacturing process related problems. In this paper, we address the problem of diagnosing failures in digital filters. It is assumed that the circuit response obtained during off-line testing of digital filters is to be used for fault diagnosis. The tests applied to the filter consist of input data patterns generated by a standard test pattern generation algorithm. We propose a design for diagnosability procedure, based on time space expansion of a digital filter, which allows one circuit node in addition to the normal filter output to be externally observable for diagnosability purposes. The diagnosis is performed by measuring the error magnitudes at the observable circuit nodes at different times during application of the test sequence.>

Most behavioral synthesis tools perform limited architectural transformations to optimize hardware.In this paper, we present a new architectural transformation scheme that changes the circuit interconnections and the descriptions of constant multipliers.The scheme is based on numerical matrix transformation algorithms that allow a given matrix to be expressed as the product of severrd matrices and achieves significant hardware savings over conventional methods.

The areas of analog circuit fault simulation and test generation have not achieved the same degree of success as their digital counterparts owing to the difficulty in modeling the more complex analog behavior.We present a novel approach to this problem by mapping the circuit and circuit-level faults to the dis- crete domain.An efficient fault simulation is then performed on this discretized circuit for the given input test waveform.

Recognizing that specification testing of analog circuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique. With the help of hierarchical fault models for parametric and catastrophic faults, and a very efficient fault simulator, our simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits. By a suitable choice of parameters in the test generator, we can either determine the best test (maximize the error between the good and the faulty responses) for every fault (resulting in a large test set), or generate the smallest test set for all the faults. Finally, fault coverage values provide a quantitative evaluation of the final test set.

Concurrent error detection in digital state variable circuits is very important, because they are often used in critical digital signal processing (DSP) and control applications where error in processed data can have catastrophic effects. Typically, error detection is performed by a small amount of additional hardware called the checking circuit. In this paper, we investigate concurrent error detection techniques for nonlinear digital circuits that compute polynomial functions of multiple variables. The novelty of our approach allows us to use the nonlinear functions to drive the check circuitry without duplicating the entire nonlinear part, while achieving high fault coverage.>

This paper presents an efficient unified approach to mixed-signal fault simulation. A common fault simulation platform is developed for continuous valued analog circuits, discrete time switched-capacitor circuits and binary valued digital circuits, by discretizing the analog circuit, using discrete models of switched-capacitor circuits and complementing the stuck-at digital fault models with comprehensive behavioral analog fault models.>

A theory for error detection in linear digital state variable systems is described. With the aid of a tool called the gain matrix, it is shown that the effect of error propagation along different paths of the circuit can be analyzed. For circuits with operator fanout, it is shown that despite the fact that single faulty operators cause multiple state variables to be erroneous, no more additional check variables are required than for circuits without operator fanout. It is further shown that hardware optimization can be performed by sharing hardware functions between the original state variable system and its error detection circuitry. The analysis is performed for both single and multiple faulty operators. A scheme for error correction that performs error correction in real time is proposed. Experimental results that illustrate the practical viability of the proposed scheme are discussed.>

The problem of concurrent error detection and fault tolerance is studied. These checksums of time-varying functions are possible because the function of a linear analog circuit can be represented mathematically by a set of matrices to which checksum codes can be applied. For the purpose of error detection, it is assumed that a fault can cause the value of a passive circuit component to deviate from its normal value, result in a line short or open, or change the operating characteristics of the active components (operational amplifiers). If the specifying parameters of a linear analog circuit change due to a fault and the failed circuit behaves as a linear system, then error correction is performed by compensating for the changed parameter values. Otherwise, partical correction is possible. Error detection and correction are performed by a small amount of hardware added to the linear analog circuit. The hardware overhead is virtually constant irrespective of the circuit size, and the sensitivity of the error detection circuit to failures can be easily calibrated.>

A greedy optimization technique for minimizing the area of linear digital systems using a combination of common subexpression elimination and modification of multiplier coefficients is proposed. Since the amount of logic required by a coefficient multiplier is dependent on the value of the coefficient, the given system is transformed, using splitting of coefficients, in such a way that the overall circuit requires a smaller area. The approach explores a much larger design space as compared to previously known techniques. The approach is the first to optimize numerically intensive digital circuits by additive decomposition of multiplier coefficients. The new synthesis scheme generates functionally equivalent but structurally different circuits with a 15 to 40% reduction in area over conventional methods, for practical circuits with DSP applications.>

A hierarchial testing approach for linear state variable digital systems based on matrix manipulation and constrained low-level test generation is reported. FEAST (functional extractor and sequential test generator) operates at the high level, where the circuit is described as an interconnection of arithmetic modules. CREST (constrained sequential test generator) operates at the low level description of the individual modules, and generates test sets satisfying constraints imposed by the high-level modules and their interconnection structure. The approach was found to perform better than automatic test generation at the gate level using existing algorithms for several large circuits.>

An approach to designing fault-tolerant linear analog system based on checksum-coded state-space representations of these systems is described. It is assumed that under fault, the values of the resistors and capacitors of the analog circuits are different from their fault-free values. Some shorts and opens and faults in the operational amplifiers are corrected as long as the faulty circuit behaves as a linear system. The hardware overhead is virtually constant irrespective of the circuit size.>

The problem of concurrent error detection in a class of linear analog systems containing second and higher order stages is discussed in this paper. Individual stages of such systems have transfer functions whose denominators contain the terms s/sup 2/,s/sup 3/,. . ., where s is the complex frequency of the transfer function H/sub i/(s) of the i'th stage. Such systems are widely used to realize a variety of analog and switched-capacitor filters and control systems. The author assumes that a fault can cause the value of a passive circuit component to deviate from its normal value, result in a short or an open line or change the operating characteristics of the operational amplifiers. A small amount of additional hardware is used to perform error detection, its size being virtually independent of the size of the circuit on which error detection is to be performed. Further, the sensitivity of the error detection scheme to changes in the component values can be easily adjusted.>

Delay fault testing of iterative arithmetic arrays (IAAs) is important because IAAs contain long critical paths and often determine the clock speed. A new approach, based on a weighted graph model has been developed that exploits the regularity of IAAs to select paths to be tested, and generates delay fault tests for those paths. The number of longest paths in an IAA grows exponentially with the dimension of the IAA, but the technique tests only a selected subset of longest paths, whose size is linear in the dimension of the IAA. A Monte-Carlo simulation was performed to ascertain the detection of delay faults in paths that were not explicitly tested. Promising results were obtained.>

A novel approach to fault location in linear digital data flow graphs is presented. The fault location scheme is simple and depends on the linearity property of these data flow graphs. Identification and replacement of the failed component allows operation of the circuit at the desired clock speed. It is shown how timing problems identified during speed testing of a class of circuits widely used in digital signal processing and control can be isolated to individual or sets of circuit components.>

The authors present a novel approach to the test generation problem for a more general class of two-dimensional iterative logic arrays (ILAs) than considered by previous researchers. For certain ILAs it is possible to find a test set whose size remains fixed irrespective of the size of the ILA, while for others it varies with array size. Given an arbitrary ILA cell truth table and a cell interconnection structure, the goal is to determine if a fixed-size test can be found. If not, then a test set whose size grows as slowly as possible with the size of the array should be found. The authors propose a new model, called the n-cube of cell states model, for representing the cell truth table and interconnection structure. The test generation problem is shown to be related to certain properties of cycles in a set of graphs obtained from this model. By careful analysis of these cycles, efficient testing schedules can be obtained. The proposed technique can be applied to unilateral as well as regular bilateral ILAs in which the bilateral direction of signal flow are restricted to lie along the horizontal axis.>

The problems of circuit partitioning and chip placement have been studied in the past. Given a circuit partitioned into chips, one can optimize the placement of the chips on a printed circuit board with regard to a given cost function. Conversely, given a placement of the chips on the board, one can optimize the partitioning of the circuit into the chips with regard to the same cost function. However, given neither the circuit partitioning nor the chip placement, we are faced with a difficult optimization problem. Our target technology is one in which the chips are unpackaged chips placed on a substrate, analogous to the printed circuit board and interconnected together with high density interconnect to realize a complex system. We propose a new approach in which the circuit is both partitioned and placed simultaneously by a simulated annealing based algorithm. Our approach is seen to yield excellent results in reasonable run times.

The testability of a class of circuits called generalized counters is investigated under a more powerful fault model than examined in earlier work. It is assumed that any number of full adders in a generalized counter can assume an incorrect function under fault, as long as the function remains combinational. The testability of the overall class of generalized counters is examined and it is shown that under a restricted fault model it is possible to detect all multiple faults with a test set that grows linearly with the number of counter inputs. It is then shown that for a subset of the class of generalized counters it is possible to detect multiple faults with a larger number of tests, linear to the number of counter inputs, when the restrictions on the fault model are relaxed.>

NCUBE applies all possible input patterns to each array cell while ensuring that the effects of incorrect transitions are observable at the array outputs. If the array is testable with a constant number of test vectors irrespective of its size (C-testable), then NCUBE generates the constant-size test set for the array. If the array cannot be tested with a constant number of test vectors, then the test size is proportional either to the number of rows or columns of the array or to the number of cells. In that case, NCUBE generates a minimal or near-minimal test set that depends on the size of the array.>

An efficient MOSFET model for accurate prediction of the drain current and the drain conductance of a short-channel MOSFET is presented. Earlier models for channel length modulation are not suitable for simulating analog circuits for which the drain conductance is important. Empirical expressions derived from measured I-V characteristics are used to fit well the behavior of drain conductance with gate and substrate bias predicted by the model, which thus overcomes the limitations of earlier models. The model was implemented in SPICE, and several simple circuits have been tested without encountering any convergence problems.>

This paper investigates the testability of a class of circuits, called counters, that perform the addition of sets of input bits of equal arithmetic weight. These circuits consist of full and half adders interconnected in an iterative manner defined by the counting process. The general class of counter circuits contain reconvergent fanouts and are not as structurally regular as one- or two-dimensional iterative logic arrays. A model for analyzing the structure of counter circuits is proposed. Several schemes for generating test sets that exploit the iterative structure of counter circuits are presented. The testability of such circuits is enhanced by imposing certain design constraints on them. Some methods for generating easily testable counter circuits are proposed. It is shown that counter circuits can always be designed to be testable with either eight or ten tests, irrespective of the input size.