The need to rapidly increase per-lane data rates to meet system bandwidth demands has led to the adoption of digital equalization schemes in wireline transceivers. However, for short reach applications, mixed-mode designs offer better power and area efficiency, especially if their complexity explosion with data rates can be alleviated. This paper presents a new hybrid linear/nonlinear equalizer that unfolds the popular recurrent equalization architecture to remove any fundamental timing constraints in the wireline receiver. The modular multi-stage architecture drastically reduces the receiver complexity and enable real-time architecture tuning to improve energy efficiency. This paves the way for continual data rate enhancement with improved circuit performance. To ensure reliable performance in advanced CMOS processes, time-domain analog signal processing is used. This choice also enables linear energy scaling with data rate and allows proportional power scaling with degree of equalization. A 3-tap realization of the receiver fabricated in 28 nm CMOS process achieved a data rate of 52 Gb/s with an efficiency of 1.0 pJ/b and BER below 1e-4 with moderate ISI where channel loss at Nyquist is less than 12 dB.

The drive for higher per-lane data rates has led to increased complexity in wireline transceiver architectures due to the need for higher-order equalization. This has the potential to result in degraded energy and area efficiency of these transceivers. A new multi-stage decision feedback equalizer (DFE) design approach that leverages speculative intersymbol interference (ISI) cancellation to achieve low complexity is proposed. A 2-tap multi-stage PAM4 DFE design example that uses lower than 35% of the components of a conventional speculative DFE, and can be applied to most channel profiles, is used to discuss the equalization capability of the proposed approach. It is also used to discuss the impact of circuit nonidealities on performance. Simulation results of the multi-stage DFE over three different channels showed matched equalization performance to the conventional designs, even as it promises higher data rates than the direct feedback DFE and drastically higher energy efficiency than the conventional speculative DFE.

High-sensitivity optical receivers enable energy-efficient solutions for high-speed optical interconnects. In this article, an analog front-end (AFE), employing a sub-Nyquist CMOS-based trans-impedance amplifier (TIA) with post-TIA equalization, is characterized to give an insight on how to design the AFE for optimizing receiver sensitivity and energy-efficiency. Thus, maximizing SNR is targeted. Sub-Nyquist TIA design tradeoffs were analyzed to study the BW limitation impact on linearity and noise. The characterization utilizes idealized NRZ/PAM-4 samplers with DFE/FFE to analyze the equalization complexity. Optimum SNR is reported for different equalizers, specifying the relaxation achieved in TIA BW requirement with respect to the desired data-rate.

Baud rate timing recovery, for which the Mueller-Muller approach is the most prominent, has become the mainstay of high speed serial links because of the simplicity of its implementation. The foundations of Mueller-Muller - Type A timing function and its propensity to lock to erroneous sampling points when applied to high order pulse amplitude modulation is studied. Using the timing error detector characteristics, the probability of the Mueller-Muller - Type A phase detector (PD) to settle to undesirable lock points is investigated. The impact of prevailing approaches to mitigate the effect of this behavior on the performance of clock and data recovery (CDR) systems is quantified, and a new low-overhead PD approach without any of their drawbacks is proposed. Simulink simulations of the CDR phase acquisition, jitter tolerance and timing margins are used to demonstrate the effectiveness of the proposed PD in achieving superior CDR performance while avoiding any of the convergence issues.

This paper does an empirical investigation of the effect of nonlinearity in time-based wireline receivers. The linearity of the voltage-to-time converter (VTC), a necessary component of the time-based receiver is simulated, and its impact on the performance of the receiver is studied. Simulation results in a 28nm CMOS process show the effectiveness of using equalization to suppress the effect of VTC nonlinearity and improve the receiver performance.

A wireline receiver complexity reduction approach achieved by using hysteretic extraction of the error for phase detection is presented in this paper. The approach is based on the utilization of the data slicers intended for speculative level detection to perform a hysteretic estimation of the error signal. Simulation results showed better jitter tolerance and better eye margin for the proposed hysteretic receiver compared to prior approaches for low loss channels, while reducing the complexity by 64%.

This paper proposes receiver complexity reduction by moving the error detection to time domain. The concept of time-based level detection is introduced and its potential to reduce false locking is explored. Simulation results are included to show the efficacy of the proposed error extraction approach.

The relation between opamp noise and the size of the level shifting capacitor in correlated level-shifting (CLS) architectures is explored. Analysis is performed for a Split-CLS switched capacitor amplification circuit, and many of the conclusions in this paper are applicable to more general CLS architectures as well. A theoretical model for noise is developed and shown to be in good agreement with simulation. It is found that for practical design values, the size of the level-shifting capacitor only weakly influences noise performance.

This paper presents a pseudo-differential zero-crossing-based circuit topology that achieves differential error suppression. The nature of the charging errors in different zero-crossing-based circuit topologies is explored and the benefits of the proposed topology are discussed. Simulation results provided confirm the differential error suppression in the proposed scheme.

An Interstage Correlated Double Sampling technique is proposed. This new technique avoids the additional thermal noise penalty and the overall feedback factor degradation introduced by the conventional correlated double sampling techniques. In the proposed architecture, a two-stage amplifier is employed and the correlated double sampling is applied to the input of the second gain-stage. The superior noise performance and the gain enhancement of the proposed architecture to the conventional CDS technique is demonstrated in this paper.