Edge computing is evolving to include heterogeneous compute nodes with distinct characteristics. Graphic processing units (GPU) and field-programmable gate arrays (FPGA) can execute demanding deep learning (DL) tasks while meeting the deadlines of time-sensitive applications. However, FPGAs require reconfiguration to execute different tasks. In this paper, we first demonstrate that FPGAs can be reconfigured in real-time. Additionally, we propose ELEVATE as a novel scheduling algorithm for reconfigurable heterogeneous edge computing platforms targeting Industry 4.0 post-production quality control. ELEVATE design focusses on optimising the reconfiguration of the FPGA unit for heterogeneous quality inspection tasks. Our simulations indicate that ELEVATE reduces task waiting time by up to two orders of magnitude and achieves energy savings of up to 25 % compared to a statically configured FPGA unit.

Cardiovascular diseases (CVDs) are currently one of the leading causes of death worldwide. Being able to detect their symptoms at early stages, even the most hidden ones, is crucial to shorten the diagnosis time and facilitate an early treatment. Currently, the use of continuous tracking systems, mainly based on wearable devices that analyze data using artificial intelligence (AI) algorithms, is being explored to automatically identify, in real time, CVDs symptoms. This could be especially relevant in lowincome countries where there is a shortage of specialized doctors. Therefore, this work focuses on analyzing the real-time execution of the state-of-the-art convolutional neural network (CNN) for heart sound segmentation (HSS) on platforms such as traditional CPU/GPU and the Fraunhofer IMS © AIRISC Core Complex (a RISC-V processor developed for AI). Results revealed that, while all implementations exploiting the CPU/GPU platform proved to be useful in real-time diagnosis from a fixed location, the AIRISC demonstrated its goodness, as a system on a chip (SoC) for a real-time wearable application, when executing a quantized version of the CNN.

Fraunhofer IMS develops and fabricates far-infrared focal plane arrays (IRFPA) using microbolometers with a pixel pitch of 17μm technology realized on top of a 0.35 μm CMOS readout integrated circuit (ROIC). The microbolometers are encapsulated by a Chip-Scale-Package (CSP) to ensure a high quality vacuum level. The CSP is realized by placing an infrared transparent lid above a solder frame surrounding the microbolometer array. To concept a wafer-level test it is very challenging to implement highly accurate electrical stimuli and a far infrared radiation source (black body) while affecting the wafer-prober handling by a non-flat wafer surface, due to the infrared transparent lids of the CSP. Accordingly, wafer-level test has been developed based on a PC which controls, by using a test program, the wafer handling of a prober, the electrical stimuli of a test hardware, and the far-infrared radiation such as the optical stimuli. Thus, the most important electro-optical parameters of IRFPAs will be measured at wafer-level: Noise Equivalent Temperature Difference (NETD), responsivity, and the percentage of the defective pixels.