In-network aggregation (INA) has emerged as a key technology to alleviate communication bottlenecks in large-scale distributed training, but its performance is often hindered by suboptimal routing. Existing INA-aware routing algorithms suffer from certain limitations: they either lack a global, multi-job coordination mechanism, or operate on incomplete network models that ignore key hardware constraints such as switch processing capacity. These deficiencies lead to network congestion and inefficient resource utilization, ultimately undermining the full potential of INA. To address these challenges, we present INARouting, a novel framework that holistically solves the multi-job hierarchical aggregation routing problem. We propose TINA, a hierarchical aggregation protocol that supports multi-job in-network aggregation. To address different deployment scenarios, we develop two variants: INARouting-Opt that provides optimal solutions for moderate-scale networks, and INARouting-Relax, a fast and effective heuristic using LP-relaxation and a greedy score-based rounding algorithm for large-scale deployments. Through extensive experiments on various scales of Fat-Tree and Spine-Leaf topologies, we demonstrate that INARouting significantly outperforms state-of-the-art methods. INARouting- Opt achieves provably optimal solutions, reducing average job completion time by up to 56% compared to existing methods. Meanwhile, INARouting-Relax outperforms existing algorithms while being 5× faster in solving time, enabling efficient routing in large-scale, dynamic environments.

网络资源的覆盖范围日益广泛, 算力资源也逐渐成为能够提供泛在计算服务的基础设施. 然而, 在广域网络, 底层网络和计算资源缺乏密切的研究或协同设计, 仍然存在计算服务调度缓慢、 数据分发不灵活、 数据传输效率低等问题. 本文提出算力感知网络(CAN)的系统架构设计, 其核心贡献在于引入感知平面来收集、 管理并综合计算和网络的信息. 这样, 感知平面、控制平面和数据平面组成一个闭环控制系统, 增强了整个系统的感知能力、 决策能力和数据转发功能. 为了使能CAN系统, 本文提出三项关键技术: 算力路由、 弹性广播和广域高吞吐传输. 本文以人工智能(AI)模型训练、 推理和离线参数传输为例, 展示CAN的适用性, 并指出未来的一些研究方向.

Off-the-shelf x86 servers are widely deployed as middleboxes in edge and public clouds, such as cloud gateways and load balancers. They follow the “run-to-completion” model and achieve parallel traffic processing by distributing packet flows across multiple CPU cores using the RSS (receive side scaling) capability of NICs. However, RSS can cause inter-core load imbalance as it conducts stateless hashing without considering the CPU core utilization. As a result, multiple heavy-hitter flows can potentially overload a single CPU core when they are hashed onto that core. In this research, we propose P4RSS, a load-aware intra-server load balancing solution that leverages the P4 data plane. Specifically, a P4 ASIC is placed in front of the CPU to perform stateful traffic load balancing among multiple CPU cores based on real-time monitoring of core utilization. In addition, flow affinity maintenance and heavy hitter throttling are also offloaded to the P4 ASIC to free up valuable CPU computing resources. P4RSS can be implemented in the form of either hyper-converged server switches or P4-based SmartNICs. Evaluation results demonstrate that P4RSS reduces the standard deviation of CPU core utilization by 22%~53% compared to RSS. This not only improves the stability of middleboxes but also allows for higher CPU utilization without overprovisioning.

The In-band Network Telemetry (INT) provides unprecedented network visibility by encapsulating fine-grained device-internal status into packet headers. Existing efforts proposed to reduce the telemetry cost can either monitor a small part of flows and links, or require complex calculation supported by programmable switches. In this paper, we propose SD-INT (Self-Driving INT), a lightweight network-wide passive INT system, which can be readily deployed based on commodity switches. The key idea of SD-INT is to reduce two dimensions of redundancy in the INT data which we have observed. Furthermore, the optimized INT is conducted in a self-driving system, adjusting the INT strategy according to the feedback of INT result history. In addition to the mechanism, we design the latency-hiding technology and a suite of efficient algorithms for flow selection and sampling ratio adaptation. These designs enable us to keep the monitoring overhead under a reasonable level, while still collecting network-wide fine-grained telemetry data. Further, we prototype and evaluate SD-INT with both large-scale simulations and testbed deployment. Experiments for both TCP(Transmission Control Protocol) and RDMA(Remote Direct Memory Access) flows show that SD-INT reduces orders of magnitude data volume while achieves similar link coverage compared with INT. Besides, compared with the relevant technologies based on programmable switches, SD-INT is competitive in reducing the data volume.

The Hybrid Total Finite Element Tearing and Interconnecting (HTFETI) method plays an important role in solving large-scale and complex engineering problems. This method needs to handle numerous matrix-vector multiplications. Directly calling the vendor-optimized library for general matrix-vector multiplication (gemv) on GPU leads to low performance, since it does not consider optimizations for different matrix sizes in HTFETI, i.e. different row and column sizes. In addition, state-of-the-art graph partitioning methods cannot guarantee load balancing for HTFETI, since the matrix size is determined by the length of the subdomain boundary. To solve the problems above, we first port gemv to the multi-stream pipeline scheme and develop a new batched kernel function on GPU, which brings 15%~30% throughput improvement and 37% average GFLOPs improvement, respectively. We also propose a multi-grained load-balancing scheme based on graph repartitioning and work-stealing, and the load imbalance ratio is down to 1.05~1.09 from 1.5. We have successfully applied the scalable HTFETI method to simulate the whole core assembly of China Experimental Fast Reactor (CEFR) for steady-state analysis, and the efficiencies of weak scalability and strong scalability reach 78% and 72% on 12,288 GPUs, respectively. As far as we know, this is the first time that HTFETI has been used in large-scale and high-fidelity whole core assembly simulation.

Structural dynamics simulation plays an important role in research on reactor design and complex engineering. The Hybrid Total Finite Element Tearing and Interconnecting (HTFETI) method combined with Newmark method is an efficient way to solve large-scale structural dynamics problems. However, the sparse direct solver and the load imbalance caused by inconsistent density models are two critical issues limiting the performance and the scalability of structural dynamics computing. For the former, we propose an efficient variable-size batched method to accelerate SpMV on GPUs. For the latter, we establish an online performance prediction model, based on which we then design a novel inter-cluster subdomain fine-tuning algorithm to balance the workload of HTFETI parallel computing. We are the first to achieve the high-fidelity structural dynamics simulation of China Experimental Fast Reactor core assembly with up to 53.4 billion grids. The weak and strong scalability efficiencies reach 91.77% and 86.13% on 12,800 GPUs, respectively.