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Joseph Friel

dblp:310/7552 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 91% Cryptographic primitives and cryptanalysis · 9%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
side-channel attack
1.322023
Invited: Pre-silicon Side Channel and Fault Analysis · DAC 2023
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK · DAC 2023
Hardware security and side channels › side-channel attack › power analysis
correlation power analysis
0.712023
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK · DAC 2023
Hardware security and side channels › fault attacks
fault injection attack
0.712023
Invited: Pre-silicon Side Channel and Fault Analysis · DAC 2023
Hardware security and side channels › side-channel attack
power analysis
0.712023
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK · DAC 2023
Hardware security and side channels › side-channel attack
profiled side-channel attack
0.712023
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK · DAC 2023
Electronic design automation › hardware verification and test
hardware verification
0.712023
Invited: Pre-silicon Side Channel and Fault Analysis · DAC 2023
Cryptographic primitives and cryptanalysis
authenticated encryption
0.212023
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK · DAC 2023
Cryptographic primitives and cryptanalysis › symmetric cryptography
lightweight cryptography
0.212023
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK · DAC 2023

Methods — techniques the papers use, named apart from their topics

power estimation · 1.3formal property verification · 1.3leakage detection · 0.7correlation power analysis · 0.7convolutional neural network · 0.7
YearPublicationVenuePosition
2023 Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK
abstract
This work presents a power side-channel analysis (SCA) of a lightweight cryptography (LWC) algorithm, XOODYAK, implemented on an FPGA. First, we perform generic leakage detection tests for two phases of authenticated encryption with associated data (AEAD) mode, namely INITIALIZE, and ABSORB. Second, we develop novel hypothetical attack models for correlation power analysis (CPA) and demonstrate a success rate (SR) of 92%/82% and minimum-traces-to-disclosure (MTD)=13K/38K on the INITIALIZE/ABSORB phases, respectively. Third, we evaluate ABSORB against Profiled SCA using convolutional neural network (CNN), and achieve SR=96%/64% and MTD=2K/16K on the test set for the same/different keys used for training, respectively. Finally, we suggest low-overhead countermeasures to protect against these SCA attacks.
Anupam Golder, Debayan Das, Santosh Ghosh, Avinash L. Varna, Majid Sabbagh, Sayak Ray, Rana Elnaggar, Joseph Friel, Daniel Dinu, Jason M. Fung
DAC8
2023 Invited: Pre-silicon Side Channel and Fault Analysis
abstract
In this work, we address the challenges of side channel analysis (SCA) and fault injection (FI) in the pre-silicon design stage, particularly for cryptographic implementations. We show that the industry perspective uncovers different challenges than those usually tackled by academia, emphasizing the need for practical and scalable solutions. We present (Side Channel Attack Testbench Emulator) SCATE, a framework for detecting and mitigating SCA vulnerabilities, leveraging industry-standard electronic design automation (EDA) software for efficient power estimation and FI simulations. Moreover, we demonstrate a significant performance increase in power simulation tools by optimizing EDA algorithms for SCA applications, resulting in faster power trace generation. Additionally, we discuss the application of formal property verification (FPV) for verifying fault injection countermeasures and present a case study on an AES S-box. These approaches enable non-security-expert designers to evaluate SCA and FI resistant designs with significant time savings. The vulnerabilities uncovered by these approaches highlight the importance of pre-silicon analysis at each design stage to produce secure application-specific integrated circuits (ASICs).
Jasper Van Woudenberg, Peter Grossmann, Avinash L. Varna, Joseph Friel, Daniel Dinu, Ronnie Lindsay, Steve J. Brown
DAC4