Achieving stable and natural locomotion in bipedal robots, comparable to that of humans and animals, remains a long-standing challenge in robotics. In this work, we propose a bio-inspired low-level control framework that streamlines the generation of naturalistic gait patterns while ensuring adaptability. Our approach begins with the design of a low-dimensional gait representation that captures key characteristics of human and animal locomotion. This representation is then integrated with the Linear Inverted Pendulum Model (LIPM) to form an abstract yet effective motion descriptor. Serving as a kinematic reference within a reinforcement learning (RL) framework, this descriptor enables the training of control policies that strike a balance between biomechanical realism and adaptability. Rather than strictly adhering to predefined gait trajectories, the learned policies dynamically adjust to optimize both stability and velocity tracking. As a result, our method enables bipedal robots to exhibit smooth, biomechanically realistic locomotion while enhancing stability and adaptability. We validate the proposed framework through real-world experiments on our bipedal robot, demonstrating its ability to achieve stable and efficient locomotion.

Memristors have emerged as promising candidates for multilevel data storage, in-memory processing, and neural networks since their intrinsic programmability of resistance states under applied stimuli has been well revealed in memristor modeling. However, the programming uncertainty arising from the inherently stochastic nature of the device itself has been overlooked in previous modeling approaches. This omission hinders the incorporation of memristor stochasticity into time-domain circuit simulation. To address this issue, we propose a behavior model that incorporates real-time programming stochasticity. Our model stands out for several attributes: 1) programming stochasticity is included and exhibited in its resistance change over time; 2) its stochastic behavior is depicted by the summation of its deterministic behaviors and a noise signal; and 3) both deterministic behaviors and noise amplitudes depending on the pulse amplitude v and the memristor resistance R are determined by sufficient characterization data of our in-house TiO2 devices in a data-driven method. Consequently, our model is validated as highly matched to the characterized memristor device in terms of time-domain resistance evolution. Additionally, the modeling process can be adapted to different memristors with significant device variations. Furthermore, the model is transformed into the standard Verilog-A style for in-circuit simulation. To demonstrate its compatibility with system-level circuit simulation, a mixed-signal CMOS circuit is designed. This circuit explores the feasibility of storing multibit data within a single memristor, while considering its stochasticity.

Abstract Liver image segmentation is an attractive topic in the diagnosis and surgical planning of liver diseases. Although deep learning methods have significantly advanced liver segmentation, existing frameworks fail to clearly determine liver boundaries, especially in medical images where various organs have similar grey levels. In this paper, the authors design a multi‐scale dense residual network (MDR‐Net) for liver segmentation, which consists of two blocks: a liver segmentation network and an edge‐aware network. In the segmentation network, the authors introduce a multi‐scale residual pooling module combining channel attention (CA) mechanism and depth‐wise separable convolution to accommodate liver scale variation. Furthermore, the authors employ an edge‐aware loss network to refine edge information and enhance feature representation, which is beneficial to guide the network to iterate towards the ground truth. The authors’ method achieves the best visualization results in qualitative evaluation. In addition, the authors’ method achieves 96.189% on 3D‐IRCADb and 96.889% on the CHAOS dataset in quantitative evaluation with respect to the dice index.

Currently, we have no practical emulation solution for analogue and mixed-signal (AMS) circuits, unlike resolutions found for FPGA digital circuit emulation. This paper presents a high Q crystal oscillator circuit emulation based on Wave Digital Filter (WDF). An analogue circuit emulation method was used based on WDFs proposed in [1] to cover the entire flow of transforming an analogue circuit from a SPICE netlist towards FPGA hardware implementation. Although the WDF has been shown to be effective for circuits with linear elements, a proper method for dealing with nonlinear components, such as MOS transistors, is required. [2] proposed a WDF model for MOS transistors that can solve the connectivity problem in traditional nonlinear WDF models while maintaining analogue emulation accuracy and efficiency. As emulation examples, Resistor-Capacitor (RC), Common Source amplifier (CS), and high Q crystal oscillator circuits were implemented in WDF and compared to their SPICE simulations for verification purposes.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

Emerging memristor-based array architectures have been effectively employed in non-volatile memories and neuro-morphic computing systems due to their density, scalability and capability of storing information. Nonetheless, to demonstrate a practical on-chip memristor-based system, it is essential to have the ability to apply large programming voltage ranges during the characterisation procedures for various memristor technologies. This work presents a 16x16 high voltage memristor characterisation array employing high voltage CMOS circuitry. The proposed system has a maximum programming range of ±22V to allow on-chip electroforming and I-V sweep. In addition, a Kelvin voltage sensing system is implemented to improve the readout accuracy for low memristance measurements. This work addresses the limitation of conventional CMOS-memristor platforms which can only operate at low voltages, thus limiting the characterisation range and integration options of memristor technologies.

The memristor, because of its controllability over a wide dynamic range of resistance, has emerged as a promising device for data storage and analog computation. A major challenge is the accurate measurement of memristance over a wide dynamic range. In this paper, a novel read-out circuit with feedback adjustment is proposed to measure and digitise input current in the range between 20nA and 2mA. The magnitude of the input currents is estimated by a 5-stage logarithmic current-to-voltage amplifier which scales a linear analog-to-digital converter. This way the least significant bit tracks the absolute input magnitude. This circuit is applicable to reading single memristor conductance, and is also preferable in analog computing where read-out accuracy is particularly critical. The circuits have been realized in Bipolar-CMOS-DMOS (BCD) Gen2 technology.