The design of low-power digital signal processing (DSP) architectures have gained a lot of attention due to their use in a variety of smart edge applications and portable devices. Recent efforts have focused on the replacement of power-hungry multipliers with various approximation frameworks such as multiplierless architectures that require only a few bit-shifts, additions and/or multiplexers when the multiplicand coefficients are known a priori. However, most existing multiplierless and approximation-based works have not been combined systematically with voltage over-scaling (VOS), which is considered one of the most effective power saving approaches, while the few that have tried, were applied to specific case studies with custom modifications. In this article, we are proposing a generic optimization framework that not only minimizes the hardware units in any time-multiplexed directed acyclic graph (TM-DAG) multiplier but also allows the reliable completion of most operations and the avoidance of random timing errors under VOS. This is achieved by synthesizing alternative coefficients that approximate well the original ones, while also activating shorter critical paths. As a result when VOS is applied, minor quality degradation occurs due to the coefficient approximations which are deterministic by design, while the gained timing slack of the new multiplicands allow us to reduce the supply voltage and circumvent the random timing errors induced by the increased delay under iso-frequency/throughput. Our experiments have indicated that when our framework is applied on fast Fourier transform (FFT) and discrete cosine transform (DCT) architectures, it results in up to 34.07% power savings, when compared to conventional multiplierless architectures, while it induces minimal signal-to-noise ratio (SNR) degradation, even when voltage is reduced by up to 20%.

The identification of patterns and changes in timeseries using the autocorrelation function (ACF) is traditionally used in several applications from communications, multimedia to remote health monitoring. Existing ACF implementations have tried to meet the throughput requirements of specific domains by mainly using time-domain approaches, however such techniques require several costly multiplications, which hinder their use in power-constrained devices, essential in emerging ACF-based edge applications. Frequency-domain (FD-ACF) approaches could reduce the computational complexity of the ACF calculation, but their use is limited in specific domains, leaving room for further power-aware algorithmic and architectural optimizations. This paper presents a framework, named ACOR, for the design of energy-efficient pipelined ACF architectures under various settings, throughput and energy requirements that vary across ACF-based applications. The proposed framework allows the quick exploration of ACF architectures for different sampling window sizes, window overlapping ratios, number of lags, and precision levels, which is impossible with the existing scattered domain-specific works. Our experimental results show that when compared with existing ACF architectures used in bio-signal analysis, linear predictive coding and telecommunications our proposed framework achieves up to 27.18%, and 51.47% reduction in the circuit area and energy consumption, respectively, with a slight throughput reduction of 8%.

This paper presents an energy-efficient short-time Fourier transform (STFT) architecture. The proposed architecture is called frequency decomposition STFT (FD-STFT) and it achieves significant computational complexity reduction by effectively re-utilizing previously computed spectrums between overlapped sampling windows. Such an algorithmic modification not only reduces the required hardware units, but also achieves low accumulative error compared to conventional approaches. In addition, the quality of the resulting spectrogram is improved by integrating an efficient Hanning windowing technique that replaces the multiplication in the time domain with a low-cost filtering in the frequency domain. For an$N=256$-point window with$R=32$overlapping samples, our results indicate that our approach achieves up-to 40.86% and 65.56% area and power savings respectively, compared to recent approaches.

Many digital signal processing (DSP) applications in multimedia, telecommunications, and artificial intelligence require several multiplications, which are considered among the most expensive arithmetic operations. To optimize these operations, several approaches have been proposed, mainly by representing multiplications with additions and bit-shifts. While these approaches may have limited the number of required adders, they have not given much attention to the overhead of multiplexers, which can grow significantly. In this paper, a comprehensive framework is presented that not only reduces the number of adders as in prior works, but also optimizes the number of multiplexers needed in modern DSP architectures. This framework is based on a new accelerated depth first search (A-DFS) algorithm that yields superior results, both for single input single output (SISO) and single input dual output (SIDO) architectures, the latter of which were not covered by existing approaches. At the initial stage of the proposed approach, all possible directed acyclic graph (DAG) multipliers are generated to produce minimum adder graphs of one or two outputs. Then, a systematic strategy to efficiently merge the produced graphs is presented, while preventing the number of multiplexers from growing exponentially as the set of multiplicands increases. Our experimental results show that when applied on several popular fast Fourier transform (FFT) and discrete cosine transform (DCT) coefficient sets, the proposed framework achieves significant savings in terms of the number of required multiplexers, leading to substantial area, power and power-delay-product (PDP) reduction, compared to existing works and a commercial synthesis tool.