Private Information Retrieval (PIR) allows clients to retrieve database entries without leaking retrieval indices, yet malicious servers seriously compromise retrieval correctness. Existing Authenticated PIR (APIR) schemes resist selective-failure attacks but rely on computational hardness assumptions. In contrast, information-theoretic PIR with Result Verification (itPIR-RV) achieves integrity without computational assumptions, yet only provides relaxed query privacy with no defense against selective-failure attacks. This paper focuses on unconditionally secure information-theoretic APIR (itAPIR) constructions. We propose the rigorous information-theoretic security definition for itAPIR with statistical privacy against selective-failure attacks and integrity as core properties, formalize the hierarchical relation between itAPIR and itPIR-RV as a relaxed variant with identical integrity but basic query privacy, and prove a conversion theorem that valid itPIR-RV schemes can be directly upgraded to secure itAPIR with no extra overhead. Our work bridges the theoretical gap, simplifies itAPIR design, and enables quantum-resistant PIR in malicious server environments.

DRAM latency remains a critical bottleneck in the performance of modern computing systems. However, the latency is excessively conservative due to the timing margins imposed by DRAM vendors to accommodate rare worst-case scenarios, such as weak cells and high temperatures. In this study, we introduce a temperature- and process-variation-aware timing detection and adaptation DRAM (TPDA-DRAM) architecture that dynamically mitigates timing margins at runtime. TPDA-DRAM leverages innovativein-situcross-coupled detectors to monitor voltage differences between bitline pairs inside DRAM arrays, ensuring precise detection of timing margins. Additionally, the proposed detector inherently accelerates the precharge operation of DRAM, thereby reducing the precharge latency by up to 62.5%. Building upon this architecture, we propose two variation-aware timing adaptation schemes: 1) a process-variation-aware adaptation (PVA) scheme that accelerates access to weak cells, mitigating process-induced timing margins, and 2) a temperature-variation-aware adaptation (TVA) scheme that leverages temperature information and the restoration truncation technique to reduce DRAM latency, mitigating temperature-induced timing margins. Evaluations on an eight-core computing system show that TPDA-DRAM improves average performance by 21.8% and energy efficiency by 18.2%.

By stacking two data channels between VDD and VSS, Charge Recycling Buses (CRBs) halve the voltage swing on interconnects, achieving significant power savings for energy-efficient on-chip data transmission. However, the middle voltage (VMID) between the two channels may fluctuate dynamically due to the diversity of input data, which significantly impacts data propagation delay and reliability. Unfortunately, existing SPICE-based simulators do not run fast enough to identify the worst-case VMID fluctuation and propagation delay, posing great challenges in CRB design. In this paper, we present a dedicated CRB Simulator for fast and accurate VMID and timing analysis. A highly condensed VMID fluctuation model, which integrates each cycles VMID changes into a single closed-form formula, is embedded in the simulator to predict VMID values at clock edges. In addition, a speed-monitoring algorithm is developed to track the continuously changing signal propagation speed under intra-cycle VMID fluctuations for accurate delay estimation. Both the VMID fluctuation model and the delay estimation algorithm involve only a small number of arithmetic operations, thus featuring remarkably low computational complexity. Compared with HSPICE, our CRB Simulator runs > 1.0×105 times faster on average across various CRB circuits, with a VMID prediction error of only 1.3mV and a delay estimation error as low as 0.6%. The significant speed improvement combined with high accuracy makes our CRB Simulator an efficient and reliable solution for VMID and timing analysis in CRB circuit design.

Long DRAM access latency has a significant impact on modern system performance. However, the improvement of DRAM access latency is limited, as the DRAM vendors reserve considerable timing margins against seldom worst-case conditions. To mitigate such pessimistic timing margins, we propose a temperature- and process-variation-aware timing detection and adaption DRAM (TPDA-DRAM) architecture. It equips in-situ cross-coupled detectors to monitor the voltage difference between bitline pairs, enabling estimation of timing margins caused by process and temperature variations. Moreover, TPDA-DRAM incorporates two collaborative timing adaption schemes: 1) a process-variation-aware timing adaption scheme (PVA) that selectively accelerates the access to weak cells, and 2) a temperature-variation-aware timing adaption scheme (TVA) that precisely adjusts timing parameters by adopting temperature information. Compared to prior art, the proposed detector reduces detection deviation by 54.8% and area overhead by 88.1%. The system-level evaluation in an eight-core system shows that TPDA-DRAM improves the average performance and energy efficiency by 20.5% and 15.0%, respectively.

Recent works introduce In-Network Aggregation (INA) for distributed training (DT), which moves the gradient summation into network programmable switches. INA can reduce the traffic volume and accelerate communication in DT jobs. However, switch memory is a scarce resource, unable to support massive DT jobs in data centers, and existing INA solutions have not utilized switch memory to the best extent. We propose DSA, an Efficient Data-Plane switch memory Scheduler for in-network Aggregation. DSA introduces preemption to the switch memory management for INA jobs. In the data plane, DSA allows gradient tensors with high priority to preempt the switch aggregators (basic computation unit in INA) from tensors with low priority, which avoids an aggregator wasting time in idle. In the control plane, DSA devises a priority policy which assigns high priority to gradient tensors that benefit overall job efficiency more, e.g., communication-intensive jobs. We prototype DSA and experiments show that DSA can improve the average JCT by up to 1.35x compared with baseline solutions.

Recently, In-Network Cache (INC) systems have been proposed to promote the performance of remote storage systems. INC offloads cache onto programmable switches between the clients and the servers, responding to clients’ data queries within a sub-RTT time. However, most existing INC solutions do not take applications’ linearizability requirement into consideration, which could lead to query errors and storage state errors in the runtime. We propose a new INC system — NetKV-L, which preserves the high-performance I/O without compromising the linearizability. NetKV-L devises a sequentiality enforcement mechanism, a PSN correction mechanism, and a response memorization mechanism to guarantee linearizability under possible unreliable network conditions. Our prototype and experiments show that NetKV-L could achieve almost the same performance as the state-of-the-art systems while additionally guaranteeing linearizability.

With the increasing of dynamic random access memory’s (DRAM) capacity, the refresh operation rapidly becomes a major concern to the performance of the current computational system. Moreover, conservative timing parameters adopted for access operations make an increasing amount of negative impact on system performance and energy efficiency. In this article, we propose an in-situ charge detection and adaptive data restoration DRAM (CDAR-DRAM) architecture, which can dynamically adjust the refresh rate and relax the constraints on access timing by removing pessimistic timing margins for PVT variations. CDAR-DRAM employs a low-cost skewed-inverter-based detector to monitor the bitline voltage in runtime and estimate real-time timing parameters of cells. Based on the detector, an adaptive refresh and restore scheme (CDAR-ref) is presented, which progressively reduces the refresh rate and partially restores cells’ voltage just enough for cells with sufficient charge, thereby optimizing both refresh and restoration operations. Moreover, a supplementary adaptive access scheme (CDAR-acc) is presented, which detects the runtime charge level of recently accessed rows and reduces access latency aggressively, benefitting workloads in a single-core system and memory nonintensive workloads in a multicore system. CDAR’s flexibility allows the two schemes to be combined. The evaluation shows that in an eight-core system, the combined scheme improves performance and energy efficiency by 15.2% and 22.6%, respectively.