Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Scouting or Majority have been proposed for the implementation of logic Computing-in-Memory based on active 1T-1R crossbar arrays. The operation reliability of these concepts critically depends on the accurate readout current distinction. In this paper, we perform experimental tests for several non-stateful logic gates based on transistor-coupled resistive devices (further denoted as 1T-1R) using HfOx as the insulating material. The focus of our investigation lies on the operation reliability and the influence of operation parameters. Based on our experimental findings, we conduct a thorough statistical analysis, assessing the reliability and outline the limitations of non-stateful 1T-1R logic functions for Computing-in-Memory.

Emerging non-volatile memories (NVMs) represent a disruptive technology that allows a paradigm shift from the conventional von Neumann architecture towards more efficient computing-in-memory (CIM) architectures. Several instrumentation platforms have been proposed to interface NVMs allowing the characterization of single cells and crossbar structures. However, these platforms suffer from low flexibility and are not capable of performing CIM operations on NVMs. Therefore, we recently designed and built the NeuroBreakoutBoard, a highly versatile instrumentation platform capable of executing CIM on NVMs. We present our preliminary results demonstrating a relative error < 5% in the range of 1 kΩ to 1 MΩ and showcase the switching behavior of a HfO2/Ti-based memristive cell.

Memristive devices offer energy and area efficient non-volatile data storage for data-intense Ternary Content Ad-dressable Memory (TCAM) architectures. However, depending on the storage implementation in the bitcell design, the matching functionality shows multiple undesired discharge effects leading to false look-up results. In particular, the ternary storage suffers during the look-up operation from a poor resistance ratio, match-line leakage and device variabilities. In this paper, we investigate the inherent, design-dependent limitations in the ternary state storage capability due to different memristive TCAM bitcell design parameters and device variabilities. We test these limits based on variability-aware device simulations and isolate crucial parameters for the optimization of memristive TCAMs.

The field of neuromorphic computing is approaching an era of rapid adoption driven by the urgent need of a substitute for the von Neumann computing architecture. NEUROTEC I: “Neuro-inspired Artificial Intelligence Technologies for the Elec-tronics of the Future” project is an initiative sponsored by the German Federal Ministry of Education and Research (BMBF for its initials in German), that aims to effectively advance the foundations for the utilization and exploitation of neuromorphic computing. NEUROTEC I stands at its successful “final stage” driven by the collaboration from more than 8 institutes from the Jiilich Research Center and the RWTH Aachen University, as well as collaboration from several high-tech industry partners. The NEUROTEC I project considers the field interplay among materials, circuits, design and simulation tools. This paper provides an overview of the project's overall structure and discusses the scientific achievements of its individual activities.