In this paper, a Class-F voltage-controlled oscillator (VCO) with low-phase-noise (PN) and ultra-low-power consumption is proposed by reactivating the common-mode (CM) coupling factor in a 1:2 transformer. Unlike conventional designs that exclusively consider the differential-mode (DM) coupling factor in 1:2 transformers, our proposed architecture effectively leverages the combined potential of DM and CM coupling factors in a single transformer. For DM operation, a novel design method is presented to efficiently guide the design of ultra-low-power VCOs. This method provides clear insights into how Class-F3resonator parameters influence the loop gain characteristics, establishing a quantitative framework for performance optimization. Regarding CM operation, the 1:2 transformer’s coupling mechanism is analyzed in detail for the first time. The analysis reveals that strategic layout optimization of the center tap can reactivate the CM coupling factor, effectively expanding the CM resonance to reduce PN. Furthermore, by incorporating a tightly coupled tertiary coil, a local oscillator signal with high spectral purity is realized. Fabricated in a 110-nm CMOS process, the proposed VCO achieves a 20.2% frequency tuning range (FTR) from 10.45 to 12.80 GHz, consuming 0.38-0.50 mW with 0.2-V power supply. The measured PN exhibits −107 and −130 dBc/Hz at 1 MHz and 10 MHz offset from a 12.80-GHz carrier, respectively, with corresponding excellent figures-of-merit (FoM) of 192 and 195 dBc/Hz, respectively.

This article presents an automated circuit topology generation and optimization method for RF low-noise amplifiers (LNAs). For circuit topology generation, a three-port small-signal model based on precomputed lookup tables (LUT) is proposed to accurately describe the transistors. Based on the model, a novel predefined building block (PBB) library for LNA is created and symbolically analyzed by three-port network parameters and noise correlation matrix. Then, graph-grammar-based tree structure generation (GTSG) is applied to efficiently realize circuit topology generation. For circuit optimization, the rule-guided non-dominated sorting genetic algorithm (RG-NSGA-II) is applied to optimize the performances of generated circuit topologies. To validate, four typical examples of X-band LNA based on a 130-nm CMOS process are presented, and the results are verified using Spectre. This method can automatically generate 936 size-free circuit topologies, even a variety of inspiring topologies. Compared to traditional NSGA-II, the RG-NSGA-II shows enhanced optimization speed in four examples, with the mean absolute percentage error (MAPE) <5% to Spectre.

A novel design method for current-mode-logic (CML) frequency divider based on${C/I} _{\boldsymbol {d}}$and${G/I} _{\boldsymbol {d}}$is proposed. The design method proposes using${C/I} _{\boldsymbol {d}}$and${G/I} _{\boldsymbol {d}}$as independent design parameters, where C and G are the equivalent capacitance and conductance of coupling pair (C cell) and negative-$\boldsymbol {g}_{\boldsymbol {m}}$pair (N cell) in CML frequency dividers. Different from the traditional design method optimizing the maximum operating frequency ($\boldsymbol {f}_{\textit {in,max} }$) by adjusting the self-resonant frequency ($\boldsymbol {f}_{\textit {SR} }$), the proposed design method directly targets$\boldsymbol {f}_{\textit {in,max} }$and output amplitude ($\boldsymbol {V}_{\textit {out} }$) to obtain the${C/I} _{\boldsymbol {d}}$and${G/I} _{\boldsymbol {d}}$and solve the size and bias current of C and N cells, which realizes efficient design. Based on the proposed design method, several design examples are provided showing less than 3% error between the simulation results and design goals, and the proposed quadrature-injection CML (QI-CML) frequency divider is implemented and proven to have an improved sensitivity curve (SC). To validate the efficacy of our proposal, a frequency divider that can switch between differential-injection (DI) and QI is designed and fabricated in 110-nm CMOS process. For QI mode, the measured locking range (LR) is 141% (5-29 GHz) while consuming 5.47 mW. The achieved two figure of merits FOM$_{\textbf {Pdc}}$and FOM$_{\textbf {A}}$are 24.1 dB and 52.8 dB, respectively, which are superior to most published works.

This paper presents a knowledge-aided automated synthesis method to design broadband power amplifiers (PAs) integrated with transformer-coupled resonators (TCRs). Different from the traditional TCR-based PA designs that focus solely on broadband load-pull matching or TCR transimpedance, the intrinsic design knowledge of the proposed method utilizes the mechanism of joint-design between PA active circuits and TCR networks. By combining this knowledge with an optimization-oriented genetic algorithm (GA), an initial TCR solution that achieves low-ripple and broadband PA output response can be rapidly synthesized, in the sense that the superior initial population, not as random as that in traditional GA, can improve the GA convergence and reduce the algorithm iterations. Simulated results show that this work achieves about 4 times speed improvement in TCR synthesis than the traditional GA. The proposed method can efficiently synthesize the optimal TCR parameters for multi-stage PA to obtain the user-defined output power within a target bandwidth. As a proof of this work, a cascode-based PA for FMCW radar application is designed in 110-nm CMOS process, aiming to realize a peak 14-dBm output power and 50% 1-dB fractional bandwidth (FBW). The measured PA large-signal performance versus frequency shows a wide 1-dB BW for${P} {_{\text {sat}}}$over 8.5-14.5 GHz (52.2% FBW) with 15.7-dBm peak value and 27% peak PAEmax at 11.5 GHz, demonstrating the efficacy of the proposed broadband synthesis mothod for PAs.