This work presents a 2-MS/s 18-bit successive-approximation-register analog-to-digital converter (ADC). Acapacitor digital-to-analog converter (CDAC) and a resistor digital-to-analog converter (RDAC) are cascaded to avoid the linearity limitation caused by parasitic capacitors on the bridge capacitor between the CDAC and the RDAC. An optimal-combination-algorithm (OCA)-based calibration is adopted to improve the linearity of the CDAC and the matching between CDAC and the bridge capacitor, and a least significant bit (LSB)-side dynamic element matching (DEM) strategy is applied to further improve the CDAC linearity. As for the RDAC, this work makes it calibration free by combining the parallel R-unit and R-2R topology. Measurement results show that the proposed ADC can achieve 91.4-dB signal-to-noise and distortion ratio (SNDR), 12.0-parts-per-million (ppm) (3.1-LSB) integral non-linearity (INL), and 174.0-dB FOMS,SNDR(including the power consumed by the calibration logic), and the worst-case INL across 25 dies improves from 72.5ppm (19.0LSB) to 18.8ppm (4.9LSB) after the OCA-based calibration and theLSB-side DEM. To the best of the authors’ knowledge, this is the first high-precision (resolution$\geq 16$bit) data converter adopting OCA-based calibration.

In this paper, a low-power capacitively coupled analog frontend with programmable high-pass cutoff frequency from 61 mHz to 3.4 Hz is proposed. The DC operating point of the input differential pair is settled by dynamic equilibrium of direct tunneling current. A DC servo loop (DCSL) based on duty-cycled operational transconductance amplifier (DC-OTA) has been implemented at the output nodes of the main frontend so that its impedance will not be affected. A minimum of 1.67 pA/V effective transconductance has been realized through the DC-OTA techniques in DCSL, which enable the frontend to achieve 61 mHz high-pass cutoff frequency with only a 10 pF on-chip capacitor. The frontend is implemented in standard$\mathbf{0.18}- \mu \mathbf{m}$CMOS process and it consumes$\mathbf{2.72} \ \mu \mathbf{A}$current in total, achieving a noise efficiency factor of 6.01 in 25 kHz bandwidth (61 mHz - 25 kHz).

This paper presents a top-to-bottom element-matching strategy based on a full-permutation bisection algorithm for data converters. By bisecting the composing elements and recombining them for a minimal weight difference, the linearity of the data converter can be significantly improved. Three different approaches have been implemented for the proposed algorithm, and they are based on linear programming, stochastic quantization, and maximal linearly independent subset (MLIS) respectively. Their pros and cons have been discussed and simulated exhaustively, and all of them have been silicon proved via capacitive digital to analog converters in 180-nm technology. Measurement results of twenty dies for each approach verified the aforementioned theoretical analysis, and all three approaches could achieve sub-30 ppm for all codes after calibration. The worst integral nonlinearity at the most significant bit after calibration can be improved from 402 ppm to 10.9 ppm, which is equivalent to a 5.2-bit boost, indicating a promising potential of the proposed matching strategy. Besides, the MLIS-based approach is the first optimal-combination-algorithm-based matching strategy that achieves$\mathcal {O}(N)$time complexity, as the authors know.

The inevitable capacitor mismatch due to the process variation is one of the major bottlenecks in high-resolution ADC (Analogue to Digital Converter) design. In this work we propose a new compensation strategy which adopts the DEM (Dynamic Element Matching) technique to conventional cyclic ADCs with minimum hardware cost. Theoretical analysis has been done first, and to the best of authors’ knowledge, it is the first time that the relation of the capacitor mismatch, output deviation and THD (Total Harmonic Distortion) has been mathematically established. Consequently, the statistical distribution of expected THD under certain mismatch can be derived. Based on that we further analyse the effect of DEM in frequency domain, which effectively performs a harmonic shaping function to the original output spectrum. Simulation results show that the DEM compensation strategy can effectively boost the worst SINAD (Signal to Noise and Distortion Ratio) Figure from 68.8 dB to 89.5 dB (99.7% yield) under 0.1% capacitor mismatch and 32× oversampling ratio scenario.

Element matching approaches based on Optimal Combination Algorithms (OCAs) are methods that try to calibrate element mismatches in data converters by rearranging the mapping relations between circuit elements and control logics. This work for the first time proposes a universal method and its corresponding Figure-of-Merit to evaluate the performance of various OCA approaches. It adopts the quantile of integral nonlinearity as the criterion and is consequently compatible with most of matching OCAs. Dynamic performance and the corresponding effective-number-of-bits (ENOB) limited by mismatches are also investigated. A critical feature of the proposed method is its robustness to the disturbance of element standard deviation as long as the standard deviation is in a reasonable region. Merits of our method have been explained and proved mathematically, and also been verified numerically by data extracted from previously reported works and their reproduction by authors, which together make this proposal more convincing and rigorous. Due to those merits, our proposed method could also help designers to specify a feasible standard deviation for circuit elements when they are designing data converters with OCAs.