Designing a bipedal robot is a complex and challenging task, especially when dealing with a multitude of structural parameters. Traditional design methods often rely on human intuition and experience. However, such approaches are time-consuming, labor-intensive, lack theoretical guidance and hard to obtain optimal design results within vast design spaces, thus failing to full exploit the inherent performance potential of robots. In this context, this paper introduces the SERL (Structure Evolution Reinforcement Learning) algorithm, which combines reinforcement learning for locomotion tasks with evolution algorithms. The aim is to identify the optimal parameter combinations within a given multidimensional design space. Through the SERL algorithm, we successfully designed a bipedal robot named Wow Orin, where the optimal leg length are obtained through optimization based on body structure and motor torque. We have experimentally validated the effectiveness of the SERL algorithm, which is capable of optimizing the best structure within specified design space and task conditions. Additionally, to assess the performance gap between our designed robot and the current state-of-the-art robots, we compared Wow Orin with mainstream bipedal robots Cassie and Unitree H1. A series of experimental results demonstrate the Outstanding energy efficiency and performance of Wow Orin, further validating the feasibility of applying the SERL algorithm to practical design.

This paper presents a coarse-fine bypass window technique to improve the energy efficiency of the successive approximation register (SAR) analog-to-digital converter (ADC) by skipping unnecessary conversion cycles when the input signal is within the bypass windows. It utilizes the time information of the MSB comparison to coarsely detect the input range without a dedicated timing budget. Based on the coarse detection results, the fine bypass window is configured by reusing the digital-to-analog converter (DAC) to accurately detect the input signal. Due to the presence of the coarse detection, the multi-window detection and its corresponding bypass operation are realized to maximize the effectiveness of the bypass window technique. In addition, the MSB-spilt switching scheme is proposed to reduce the DAC switch-back energy. A prototype 8-bit SAR ADC equipped with the proposed technique is fabricated in a 65-nm CMOS process. At a 350-MS/s sampling rate with a Nyquist input, the measured signal-to-noise-plus-distortion ratio (SNDR) and spurious-free dynamic ranges (SFDR) are 44.9 dB and 63.9 dB, respectively. At a supply voltage of 1.2 V, the ADC consumes power of 1.58 mW with the full-scale sinusoidal input signal. The ADC achieves an effective number of bits (ENOB) of 7.17 bit, resulting in a figure-of-merit (FoM) of 31.3 fJ/conversion-step. The ADC core occupies an active area of 0.0096 mm2.