This paper presents the design and implementation of a hardware-based memory game developed on an FPGA platform to promote cognitive stimulation among older adults. The game features a 3×3 LED and switch matrix that displays pseudo-random light patterns that users must recall and replicate. To enhance randomness, a seed is extracted from ambient electromagnetic noise using an Analog-to-Digital (ADC) and fed into a multi-Linear Feedback Shift Register (LFSR) pseudo-random number generator (PRNG). The PRNG employs XOR-combined LFSRs initialized with non-overlapping seed transformations to ensure statistical independence. A finite state machine (FSM) governs the game logic, translating 9-bit PRNG outputs into spatial LED patterns and evaluating user input for correctness. Statistical analyses of PRNG outputs, using normality tests and Central Limit Theorem-based smoothing, verify the Gaussian conformity and entropy quality of generated sequences. The fully integrated system includes custom PCBs for ADC input, a mechanical button interface, and an LED display, housed in a 3D-printed enclosure. Results from both simulation and hardware validation confirm the system's effectiveness in generating high-quality randomness and delivering a simple, tactile, and accessible cognitive exercise platform.

This project focused on the development of a Tetris-like game that incorporates a pseudo-random number generator (PRNG) implemented on a Field Programmable Gate Array (FPGA) to enhance the gameplay experience. By utilizing a hardware-generated seed instead of relying solely on software-based randomness, the project introduces a novel approach to determining the sequence in which Tetris blocks appear on the screen. This integration of hardware and software not only adds a layer of complexity to the game but also showcases the seamless real-time communication between a digital system powered by an FPGA and an interactive Python-based gaming application. Overall, this project represents a significant step forward in the realm of game development by showcasing the potential of integrating hardware and software technologies to enhance gameplay and create more engaging experiences for players. The fusion of FPGA-driven hardware components with a Python-based game exemplifies the innovative spirit driving advancements in the gaming industry, paving the way for future developments that blur the lines between virtual and physical gaming environments.

This paper introduces a novel hardware-based solution for generating one-time passwords (OTPs) using a field-programmable gate array (FPGA). By leveraging real-world analog noise sources like light, temperature, and sound sensors, the system ensures a high level of entropy to seed the random number generation process in a dedicated FPGA chaotic Chua's circuit. The design of this OTP generator is capable of producing secure 5-digit OTPs ranging from 00000 to 99999. These OTPs can serve various purposes, such as wireless applications when transmitted to an ESP32 microcontroller or authentication in access control systems. By integrating these OTPs directly into access control systems, organizations can enhance their security measures significantly. This integration allows for seamless and secure authentication processes, ensuring that only authorized individuals gain access to restricted areas. The proposed approach prioritizes high randomness and resistance to prediction, essential characteristics for secure embedded systems. By incorporating multiple noise sources and utilizing FPGA technology, the OTP generator guarantees a robust level of security. Overall, the hardware-based OTP generator presented in this paper stands as a reliable and innovative solution for enhancing security in embedded systems.

This paper proposes a cost-effective Cryptographically Secure Random Number Generator (CSRNG) utilizing a Field-Programmable Gate Array (FPGA) integrated with a Geiger counter. The front end of this system is designed to capture ambient radioactivity through a Geiger counter system that emits pulses in response to such environmental stimuli. To complement this setup, a neoTRNG-based ring oscillator RNG is incorporated to enhance the randomness of the generated numbers. By combining these elements, the CSRNG can achieve a high level of unpredictability crucial for cryptographic applications. Moving to the system's backend, utilizing the BLAKE2s hash function is pivotal in counteracting any potential biases introduced by the frontend components. This hashing function ensures that the output random numbers remain robust and secure, free from discernible patterns or vulnerabilities. In essence, the methodology outlined in this paper offers a comprehensive guide to conceptualizing and implementing a cost-effective CSRNG. The challenges inherent in generating cryptographically secure random numbers can be effectively navigated through a meticulous integration of hardware components and cryptographic techniques. This approach sheds light on the intricate processes in creating a reliable source of randomness, essential for safeguarding sensitive information in various digital systems.

The project is about integrating biometric security, hardware-based randomness, and symbolic visualization through tarot for a unique user experience. It utilizes a field-programmable gate array (FPGA) for biometric authentication using fingerprint input to enhance security. Sensitive data is encrypted within the FPGA, ensuring tamper resistance and mitigating threats such as replay attacks. The system utilizes the entropy from the fingerprint as a seed for a pseudorandom number generator (PRNG) to select a tarot card displayed on a Raspberry Pi and a narrative. The project explores the fusion of digital security and human meaning by combining secure biometrics, hardware-accelerated cryptography, and symbolic storytelling. It aims to provide personalized authentication, interactive installations, and secure entertainment interfaces for users. A custom enclosure CAD design was developed for the FPGAintegrated biometric system to improve user-friendliness. The design focused on touch-based interaction using a touchscreen and fingerprint scanner to simplify the user interface and enhance user enjoyment. This approach allowed the team to concentrate on perfecting the PRNG code rather than dealing with moving parts and manual updates for user instructions. The Hénon Map-based PRNG is implemented in the FPGA for real-time applications.

This paper presents the implementation of a hardware pseudo-random number generator (PRNG) using multiple linear feedback shift registers (LFSRs) for generating pseudo-random numbers and ambient electromagnetic noise for seed generation. The PRNG algorithm is deployed on a Digilent CMOD A7 field-programmable gate array (FPGA) board, producing 16-bit random numbers at a frequency of 50 kHz, which are then displayed on a 7-segment display. To facilitate the transfer of generated numbers to a laptop for further use in different applications, a dedicated high-speed UART with a baud rate of 1,152,000 is designed. The performance and effectiveness of the PRNG are evaluated in this setup.