This article presents a fully integrated CMOS rectifier with dual-band (0.9/1.8 GHz) harvesting capability and wide input power ($P_{\mathbf {IN}}$) operational range, targeting on-chip ambient RF energy harvesting (AREFH) applications. The proposed work enhances the performance by addressing two primary PCE’s dynamic range (PDR) limiting loss mechanisms: reverse current loss ($P_{\mathbf {LO-REV}}$) and impedance mismatch reflection loss ($P_{\mathbf {LO-REFL}}$).$P_{\mathbf {LO-REV}}$is mitigated using a six-/nine-stage extension technique. At the same time,$P_{\mathbf {LO-REFL}}$is reduced through a fully integrated dual-domain impedance matching network (IMN) employing series and shunt resonant techniques. Implemented in 65-nm CMOS, the proposed prototype occupies an active area of 0.23 mm${}^{\mathbf {^{2}}}$and was experimentally validated via on-wafer probing. Measurement results demonstrate the peak power conversion efficiency (PCE) of 43.6% at 0.9 GHz and 47.1% at 1.8 GHz under a 100-k$\Omega $load. Moreover, the proposed rectifier achieves a 15-dB PDR at both harvesting frequencies, representing the widest PDR among prior single-band and multiband fully on-chip works, thereby highlighting its competitiveness for practical ARFEH applications.

In this paper, we present a fully integrated dual-dimensional reconfigurable charge pump (DDR-CP) for energy harvesting (EH) applications. EH systems often encounter significant input voltage variations due to changing environmental conditions, posing a challenge for conventional CPs, which are efficient only at discrete input-to-output voltage ratios. This limitation restricts their performance and efficiency over a wide power dynamic range (PDR). To address this, the proposed DDR-CP incorporates a dual-dimensional reconfiguration approach, optimizing operating frequency and CP stage configuration to maximize system efficiency across varying input and load conditions. A novel frequency tuning mechanism,termeddynamic source feed, is devised. Also, a mathematical analysis of dominant power losses over a wide PDR is derived, providing a robust design guideline for CP optimization. Fabricated in a 65-nm CMOS process, our DDR-CP integrates a total on-chip pumping capacitor of 176 pF within a compact active area of 0.286 mm2. The DDR-CP supports tri-mode operation, handling input voltages from 0.21 V to 0.7 V, and delivers up to$40~\mu $W of output power. Measurement results demonstrate a peak PCE of 73% and an average PCE ranging from 30% to 70% across the entire input range, validated under a 55-K$\Omega $output load.

This article presents a fully integrated tri-band RF energy harvesting system (RFEH) in 65-nm CMOS technology. The system is designed to harvest ambient RF energies at 900 MHz, 1.9 GHz, and 2.4 GHz through a tri-band impedance matching network (IMN), cross-coupled differential-drive (CCDD) rectifier, and an output voltage monitoring circuit to limit the rectified output voltage to 3.3 V. The system achieves a power conversion efficiency (PCE) of over 30 % across all three frequency bands with a peak of 42.8 %. Furthermore, the system exhibits a peak sensitivity of -20 dBm at an output DC voltage of 1$V$output.

This article describes a fully integrated CMOS radio frequency energy-harvesting (RFEH) front end. It features an on-chip stacked step-up transformer integrated with a cross-coupled differential drive (CCDD) rectifier to enhance the input sensitivity. The transformer also serves as an on-chip balun for the CCDD rectifier. The CCDD rectifier innovates a gate-biasing technique and realizes coupling capacitors at the end of each stage to increase the subsequent stage biasing. Here, our RFEH front end operating at 900 MHz achieves an improved sensitivity of −20 and −19.2 dBm at the 1-V output for no-load and a 1-$\text{M}\Omega $load, respectively.