Leveraging the intellectual property (IP) core is a widely adopted strategy to expedite the development of new products within modern System-on-Chip (SoC) architectures. In today’s competitive market, reusing and sharing IP cores can significantly shorten the time-to-market for SoC designs. However, this practice also introduces security problems, such as IP piracy and overuse. Watermarking is one of the most popular methods to combat IP counterfeiting. Nevertheless, the current state-of-the-art watermarking approaches often overlook the threat posed by rogue SoC design houses and frequently require physical access to the target IP in the SoC for watermark authentication. To address these issues, this paper proposes GEM-Water, an effective IP/SoC-agnostic watermark verification mechanism that utilizes the electromagnetic (EM) radiation emitted by an IP within a packaged SoC to verify the watermark during SoC boot-up. Based on secret authorship information, the functional Finite State Machine (FSM) of the target IP is modified and subsequently translated into an EM signature. This signature can later be extracted using a near-field EM probe during SoC boot-up. With the assistance of such EM side-channel analysis, GEM-Water can authenticate the watermark without the need for physical access to the target IP itself. To validate the robustness and viability of GEM-Water, experiments were conducted on various AMD Xilinx 7 series and Microsemi FPGAs, demonstrating watermark detection accuracy consistently exceeding 95% across different benchmarks.

Intellectual property (IP) core reuse serves as a key factor to the rapid development of modern system-on-chips (SoCs) by minimizing time-to-market and manufacturing cost. However, it is crucial to prevent security risks such as IP piracy and over-use while allowing IP reuse. IP watermarking is a viable solution to safeguard the copyright of IP cores through their unique identification. In this article, we introduce PSCMark as an innovative technique for authenticating IPs through the power side-channel characteristic using clock gates. PSCMark seamlessly incorporates a power signature with minimal alterations to the IP core. This is accomplished by leveraging the existing clock gates to alter the dynamic power consumption within the IP (in an SoC) based on a specified challenge. This sharp variation in power attributes upon watermark activation facilitates IP authentication in SoC. Our experimental results show that PSCMark can be robustly/effectively verified, even with the interference emanating from the rest of the functional cores in complex SoCs. We evaluate our technique on several SoC benchmarks of varying size (i.e., MIPS, openMSP430, OR1200) and demonstrate its effectiveness in proving IP ownership with high detection resolution. We also provide silicon validation by implementing PSCMark across these benchmarks using the Artix-7 FPGA board. Furthermore, PSCMark ensures a subtle and obfuscated watermarking of IP cores, enhancing its resistance to detection, removal, or modification.

With the ever-increasing re-use of intellectual property (IP) cores in modern system-on-chips (SoCs), it is crucial to prevent security risks such as IP piracy and overuse. Considering that IP watermarking is a potential solution to the copyright protection of IP cores, this paper proposes PSC-Watermark as a power side-channel-based IP authentication methodology using clock gates. PSC-Watermark embeds a power signature with very minimal modification to the IP core. It is done by reusing the existing clock gates to modify the dynamic power consumption inside the IP (in an SoC) based on an applied challenge, and it generates a unique power trace that works as a signature of the IP. Our experimental results show that this power signature can be robustly/effectively verified, even with the interferences emanating from the rest of the functional cores in complex SoCs. We evaluate our technique on several benchmarks of varying size (i.e., MIPS, openMSP430, or1200) in the presence of multiple non-watermarked cores operating in parallel and obtain > 90% confidence rate in proving the ownership of each watermarked IP core. Furthermore, the IP cores are watermarked in a subtle and obfuscated way with < 4% overhead, which makes the proposed technique hard to detect, remove or modify.

With the increased complexity of integrated circuits (ICs) and the fabrication processes at lower technology nodes, the semiconductor industry has largely shifted to a horizontal business model to minimize time-to-market and manufacturing costs. Due to outsourcing, the design house and third-party intellectual property (IP) owners lack control over the fabrication process, which can result in IP piracy, overuse, and counterfeiting. Watermarking is an approach to trace pirated parts back to the source by uniquely identifying IPs. In this paper, we introduce a novel watermarking technique, called ADWIL, using specific features and characteristics of the analog and mixed-signal (AMS) IP cores without modifying the target IP circuitry or its internal structure. Since the IP core remains unaltered, the watermark is very hard to detect and impossible to remove. Our experimental results on different op-amps demonstrate that watermark can be extracted reliably from target IP cores by using ADWIL.