Jimin Koo

dblp:314/4939 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2024
0009-0009-9545-4905ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 4 since 2021
YearPublicationVenuePosition
2024 A 72-channel Resistive-sensor Interface IC with High Energy Efficiency and a Wide Input Range
abstract
This paper presents a 72-channel resistive-sensor interface integrated circuit (IC). The proposed IC includes 8 sensor oscillators and 8 time-to-digital converters (TDCs), and each set of a sensor oscillator and a TDC is time-multiplexed to measure from 9 sensors. Consequently, it attains impressive energy efficiency of 310 pJ per channel. Employing a time-domain interface approach, the IC directly converts sensor resistance into time, extending its measurement capabilities up to 10 MΩ. It also takes advantage of a high-energy-efficiency phase-locked loop (PLL), resulting in a high signal-to-quantization-noise ratio (SQNR) that reaches the intrinsic signal-to-noise ratio (SNR) of the sensor oscillator. This results in an effective number of bits (ENOB) of 9.3 bits when 310 pJ is consumed for each channel. The ENOB can be adjusted through external FPGA control, and the maximum ENOB achieved is 14.1 with an oversampling ratio (OSR) of 256. The proposed IC, designed and fabricated in a 180-nm CMOS process with an active area of 0.015mm2, consumes only 15.07 μW per channel, resulting in a channel-specific Walden figure of merit (FoM) of 0.48 pJ per conversion step. Furthermore, by adjusting the OSR, the IC achieves an outstanding Schreier FoM of 159.8 dB in scenarios requiring high resolution.
Sunglim Han, Hoyong Seong, Sein Oh, Jimin Koo, Hanbit Jin, Hye Jin Kim, Sohmyung Ha, Minkyu Je
ISCAS4
2024 A Reconfigurable Multimodal Sensor Interface IC Based on Direct-Conversion ΔΣ Modulator Structure
abstract
This paper presents a ΔΣ-modulator-based reconfigurable multimodal sensor interface integrated circuit (IC), offering a novel approach to the multimodal measurement of voltage, capacitive, and current signals. A direct-conversion structure is employed in the multimodal sensor interface, and its reconfigurable ΔΣ modulation scheme ensures compact die area, high energy efficiency, and enhanced dynamic range. Fabricated in a 180-nm CMOS process, the multimodal sensor interface achieves measured dynamic ranges of 70.6 dB, 97.8 dB, and 60.0 dB for voltage, capacitance, and current modes, with measured power consumptions of 22.2 μW, 23.0 μW, and 37.7 μW, respectively. The proposed system demonstrates significant improvements in the dynamic range relative to power consumption compared to other state-of-the-art multimodal sensor interface IC designs.
Jimin Koo, Yoontae Jung, Sein Oh, Sunglim Han, Sohmyung Ha, Minkyu Je
ISCAS1
2024 An Area-Efficient, DC-Coupled VCO-Based CT ΔΣM with Input-TR-DAC for Neural Recording
abstract
This paper presents a neural recording integrated circuit (IC) with a DC-coupled VCO-based continuous-time ΔΣ modulator with a novel input transistor ΔΣ digital-to-analog converter (DAC) technique. The input transistor operating as a transconductor is implemented in the form of a transistor DAC (TR-DAC) consisting of multiple transistors, which enables the ΔΣ operation according to the output digital code. Notably, this topology isolates the input from the feedback loop, resulting in exceptionally high input impedance. Furthermore, the input transistor itself functions as a ΔΣ DAC, eliminating the need for additional passive or active DAC components. Consequently, the proposed design significantly reduces area consumption, enabling its application to future scalable brain-machine-interface (BMI) systems. The proposed IC designed in a 0.18-µm CMOS process consumes only 4.7 µW with a bandwidth of 5.12 kHz. Thanks to its DC-coupling characteristics and small input parasitic capacitance, the design achieves a high input impedance of 1.26 GΩ. Furthermore, the chip occupies a compact area of 0.054 mm2per channel, while the input TR-DAC used as a ΔΣ DAC occupies only 0.008 mm2.
Woobean Lee, Yoontae Jung, Hyuntak Jeon, Jimin Koo, Sein Oh, Soon-Jae Kweon, Minkyu Je
ISCAS4
2023 A Sub-aF Super-High-Resolution Capacitance-to-Digital Converter with a Bandpass ΔΣ ADC
abstract
A super-high-resolution capacitance-to-digital converter (CDC) capable of reaching sub-aF capacitance resolution has been proposed. The CDC employs a continuous-time (CT) low-noise capacitance-to-voltage converter (CVC) followed by a high linearity bandpass$\Delta\Sigma$ADC$(\text{BP}-\Delta\Sigma \mathrm{M})$without frequency demodulation. By avoiding demodulation and utilizing a narrow-band sensing technique, the proposed CDC achieves a sub-aF capacitance resolution while expanding the input capacitance range through a coarse C-DAC calibration loop. The proposed circuit has been implemented in a$0.35-\mu \mathrm{m}$CMOS process with a 3.3 V power supply voltage. The CDC shows a capacitance resolution of 0.98$\text{aF}_{\text{rms}}$, with a capacitance range of 3.1 pF, while consuming 4.16 mW.
Yoontae Jung, Soon-Jae Kweon, Hyuntak Jeon, Jeongeun Lee, Youngin Kim 0001, Sein Oh, Jimin Koo, Minkyu Je
ISCAS7