A methodology is suggested for the study of integrated-circuit manufacturing limits. It is based on a hierarchical view of manufacturing detractors and associates limits with levels in this hierarchy. The methodology is illustrated with examples of steady-state, theoretical, and process limits at today's state of the art as well as example projections to future manufacturing at what may be near the limits of complementary metal-oxide-semiconductor (CMOS) scaling. There are also some speculations on possibilities beyond these limits.

The future of microelectronics will be determined largely by the success of the semiconductor industry in continuing to exploit the "productivity engine". The cycle of this engine is: 1) exponential trends in technology and productivity improvement, which enable 2) expanding markets and revenues, which enable 3) larger research and development (R&D) and manufacturing investments, which, in turn, enable 1). This paradigm has served us well for almost four decades, and the semiconductor industry is probably unique in maintaining such a steep performance/price improvement trend for its products over such a relatively long period. Agriculture has shown improvement over a longer period (thousands of years) but at a much slower pace. Other industries have enjoyed occasional step-function advances, but not on a regular basis spanning several decades. Of course, there is a diversity of opinion about how much longer the fundamental trends (e.g., "Moore's law") can persist. In this paper, we will discuss some of the challenges and opportunities associated with the extension of these trends and indulge in some speculation about potential future scenarios in microelectronics business and technology.