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EDBT 2026 Demo / reviewers in the wild / expert

Tokuo Kure

dblp:314/5189 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Memory systems · 38% Hardware reliability and fault tolerance · 12%

Topics — the 2 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › memory circuit design
memory cell design		 0.011999
Single-electron memory for giga-to-tera bit storage · Proc. IEEE 1999
Memory systems
non-volatile memory		 0.011999
Single-electron memory for giga-to-tera bit storage · Proc. IEEE 1999
YearPublicationVenuePosition
1999 Single-electron memory for giga-to-tera bit storage
abstract
Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/single-electron-memory hybrid integration and its positioning among various memory architectures.
Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi 0002, Tokuo Kure, Koichi Seki
 Proc. IEEE8