As voltage margins continue to shrink in modern high-performance ICs, circuits become increasingly vulnerable to power supply noise, making the minimum supply voltage ($V_{\text {min }}$) a critical metric for reliable operation. These voltage fluctuations arise from the multi-level characteristics of the power delivery network (PDN), whose frequency-dependent impedance induces multi-order voltage droops under dynamic loads. This paper presents a systematic framework for understanding and predicting $V_{\text {min }}$ failures in PDNs through multi-order droop signatures. We examine how varying input current profiles affect the relative impact of each PDN level and conduct a comprehensive statistical study to quantify the relationship between droop characteristics and multi-level contributions to $V_{\text {min }}$. A machine-learning model is further developed to rapidly and accurately predict multilevel contribution ratios from input current profiles and droop signatures, offering insights into $V_{\text {min }}$ failures and facilitating efficient PDN optimization for improved power integrity.

High-speed serial links are crucial for data transmission in high-performance systems, where increasing data rates demand robust transmitter (TX) performance. Maintaining signal and power integrity (SI/PI) in highly nonlinear TXs is essential, especially as lower power supply levels heighten their sensitivity to power supply noise (PSN). The interaction between PSN and input signals through coupled pathways further complicates PI-SI co-analysis of TXs. In this work, we propose a physical-inspired TX model, a Contrastive Masked Decoder with Feature-Wise Linear Modulation (CD-FiLM), for PI-SI co-analysis of high-speed TXs. We identify that the input and output features of the circuit correspond to different modalities under the same circuit state. By incorporating contrastive learning into a supervised learning framework, CD-FiLM aligns input and output to the same circuit-state space, enhancing robust feature representations, and thus improving the accuracy of noisy output signal predictions. We design an effective feature fusion module that captures signal and circuit interactions by modulating the input and PSN signals with circuit parameters, forming a comprehensive circuit state representation. To efficiently capture the temporal dependencies within the highly nonlinear TX output signals, we use masked data modeling for structural learning of long-sequence signals, employing a masked decoder for efficient parallel decoding. Experimental results show that CD-FiLM achieves efficient PI-SI co-analysis for TXs in high-speed links operating up to hundreds of GHz, producing eye diagrams with mean relative errors of 0.10-2.24% and 100–134× speedup.

With escalating power integrity challenges in advanced technologies, acquiring accurate dynamic power supply noise through Dynamic Voltage Drop (DVD) analysis becomes increasingly demanding. As noise margins shrink, the use of Value Change Dump (VCD) files for precise DVD analysis is indispensable but computationally expensive. Furthermore, the substantial storage requirements of VCD files, which record digital waveforms from logical simulations, pose significant challenges. In this article, we propose a machine learning (ML)-assisted VCD processing framework to accelerate DVD analysis and improve data efficiency. Transitions recorded in VCD files are mapped to a Physical Design-Aware Circuit Hierarchy Tree (CHT) for efficient feature extraction. These features are leveraged by an XGBoost-based predictor to identify critical vector time windows within the VCD, significantly reducing simulation complexity. Additionally, Huffman encoding is applied to compress signal names, further optimizing storage utilization. Experimental results show that DVD analysis using our profiled VCD files achieves a speedup of approximately 3.53× with an error margin of only 3.89%.

Electro-thermal coupling has become a concerning issue in 3D integrated circuit (IC) designs. Conventional electro-thermal co-simulation methods rely on iterative solutions of electrical and thermal partial differential equations (PDEs) using numerical techniques, which are computationally expensive and time-consuming. To address this, in this paper, we propose a novel electro-thermal co-analysis framework based on physics-informed neural networks (PINNs) with coarse-to-fine models. The coarse-grained models first predict the electrical potential and temperature distributions of the entire circuit under various boundary conditions, while the fine-grained models provide enhanced resolution for regions of interest. Additionally, we introduce an efficient training strategy that accelerates convergence. Experimental results show that the proposed framework achieves high accuracy with 0.10-0.19% mean relative error and 3-4 orders of magnitude improvements in efficiency compared to the commercial tool.

Chiplet technology has recently emerged as a promising solution to improving chip performance through the modularization of complex designs and communication facilitated by high-speed interchiplet serial links. However, the increasing on-package routing density and data rates of these links introduce complex signal and power integrity challenges, surpassing those encountered in traditional large monolithic chips. Addressing these complexities with efficient analysis and design tools is crucial for maintaining design robustness. In this article, we propose SPIRAL+: signal-power integrity co-analysis framework for high-speed interchiplet serial links validation. The framework employs machine learning (ML) to construct transmitter models and utilizes an impulse response extraction method for modeling the channel and receiver. It then performs signal-power integrity co-analysis through a novel double-edge response-based method, leveraging the developed equivalent models. Additionally, an efficient ML model is crafted to accurately predict eye diagram metrics. The analysis provides valuable insights for design optimization. Experimental results show that SPIRAL+ achieves eye diagrams with a mean relative error of 0.07%–7.47%, while realizing a speedup of$31\times $–$326\times $over traditional commercial tools.

High-speed serial links are essential for low-latency, high-bandwidth communication in data-intensive systems. Signal integrity (SI) of transmitters (TXs) directly impacts transmission quality of the links, while TXs' delay also introduces timing mismatches that degrade link integrity. In this paper, we propose LiTformer, a Transformer-based model for efficient SI analysis of high-speed link TXs, featuring a non-sequential encoder and a multi-head Transformer decoder to incorporate link parameters and capture long-range dependencies. By adopting a nonautoregressive approach, it enables parallel sequence prediction. We also introduce an ANN-based delay model for fast TX delay estimation. Considering link factors including crosstalk in multiple-link systems, LiTformer enables accurate and fast long-sequence signal prediction at high data rates, achieving efficient SI analysis for TXs. Experimental results show LiTformer achieves 437-996 × speedup in eye diagram prediction over SPICE, with mean errors of 0.15-1.57%. It supports 4-bit signals at Gbps data rates for single-ended and differential TXs, including NRZ and PAM4 formats. The delay model predicts TX delay achieving a speedup of four orders of magnitude with errors of 0.86-2.69%.

Emerging domains, such as artificial intelligence, 5G mobile, and automotive, are increasingly reliant on high-speed circuits for efficient processing, in which achieving high operating frequencies and data rates is crucial to enable productive data exchange and rapid responses. High-speed data as well as low noise margin in the high-speed serial links call for efficient models of drivers. In this article, we propose a fast machine-learning-driven macromodel for high-speed drivers, which can efficiently capture the nonlinear characteristics of drivers considering dynamic supply noise with low model complexity. A decoupling-superposition strategy is employed to effectively calculate the impact of power supply noise. Additionally, we introduce a piecewise-segmented method for macromodel solving to further enhance the speed of model utilization. Experimental results demonstrate that compared to HSPICE, the proposed macromodel achieves up to$50\times $–$1200\times $speedup while maintaining sufficient accuracy, even for signals with GHz data rate.

Chiplet has recently emerged as a promising solution to achieving further performance improvements by breaking down complex processors into modular components and communicating through high-speed inter-chiplet serial links. However, the ever-growing on-package routing density and data rates of such serial links inevitably lead to more complex and worse signal and power integrity issues than a large monolithic chip. This highly demands efficient analysis and validation tools to support robust design. In this paper, a signal-power integrity co-analysis framework for high-speed inter-chiplet serial links validation named SPIRAL is proposed. The framework first builds equivalent models for the links with a machine learning-based transmitter model and an impulse response based model for the channel and receiver: Then, the signal-power integrity is co-analyzed with a pulse response based method using the equivalent models. Experimental results show that SPIRAL yields eye diagrams with 0.82-1.85% mean relative error, while achieving $18-44 \times$ speedup compared to a commercial SPICE.

High-speed serial links are fundamental to energy-efficient and high-performance computing systems such as artificial intelligence, 5G mobile and automotive, enabling low-latency and high-bandwidth communication. Transmitters (TXs) within these links are key to signal quality, while their modeling presents challenges due to nonlinear behavior and dynamic interactions with links. In this paper, we propose LiTformer: a Transformer-based model for high-speed link TXs, with a non-sequential encoder and a Transformer decoder to incorporate link parameters and capture long-range dependencies of output signals. We employ a non-autoregressive mechanism in model training and inference for parallel prediction of the signal sequence. LiTformer achieves precise TX modeling considering link impacts including crosstalk from multiple links, and provides fast prediction for various long-sequence signals with high data rates. Experimental results show that LiTformer achieves 148--456× speedup for 2-link TXs and 404--944× speedup for 16-link with mean relative errors of 0.68--1.25%, supporting 4-bit signals at Gbps data rates of single-ended and differential TXs, as well as PAM4 TXs.

Due to the mismatch between the package scaling and the relentless silicon technology scaling, the limited power supply bumps have to bear more stresses on bump reliability. A too high through-bump (TB) current may induce increased thermal and mechanical issues, thereby damaging the integrity of the solder joint microstructure. Thus, it is critical to analyze the TB current under different test scenarios at sign-off to ensure bump integrity. Since the full chip power delivery verification (PDV) needs to solve a linear system with billions of nodes, it is then very time- and resource-consuming to repeatedly conduct such bump integrity check during ECO. In this article, we present a fast TB current estimation methodology for PDV, which can significantly reduce the computational complexity while maintaining accuracy. The experimental results demonstrate that the proposed methodology can achieve very high accuracy with a relative error of around 0.6% and a maximum error of around 1.5% across four different designs with 1–2 orders of magnitude speed-up.

Grasping has long been considered an important and practical task in robotic manipulation. Yet achieving robust and efficient grasps of diverse objects is challenging, since it involves gripper design, perception, control, and learning, etc. Recent learning-based approaches have shown excellent performance in grasping a variety of novel objects. However, these methods either are typically limited to one single grasping mode or else more end effectors are needed to grasp various objects. In addition, gripper design and learning methods are commonly developed separately, which may not adequately explore the ability of a multimodal gripper. In this article, we present a deep reinforcement learning (DRL) framework to achieve multistage hybrid robotic grasping with a new soft multimodal gripper. A soft gripper with three grasping modes (i.e.,enveloping,sucking, andenveloping_then_sucking) can both deal with objects of different shapes and grasp more than one object simultaneously. We propose a novel hybrid grasping method integrated with the multimodal gripper to optimize the number of grasping actions. We evaluate the DRL framework under different scenarios (i.e., with different ratios of objects of two grasp types). The proposed algorithm is shown to reduce the number of grasping actions (i.e., enlarge the grasping efficiency, with maximum values of 161.0% in simulations, and 153.5% in real-world experiments) compared to single grasping modes.