Demo Data from EDBT 2026 / reviewers in the wild / expert
Andrew Merczynski-Hait
dblp:314/7073
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 75% Electronic design automation · 25% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA accelerator |
0.6 | 1 | 2022 | PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development · ASPLOS 2022 |
Reconfigurable computing and FPGAs
FPGA compilation |
0.6 | 1 | 2022 | PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development · ASPLOS 2022 |
Electronic design automation
high-level synthesis |
0.6 | 1 | 2022 | PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development · ASPLOS 2022 |
Reconfigurable computing and FPGAs › FPGA compilation
incremental compilation |
0.6 | 1 | 2022 | PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development · ASPLOS 2022 |
Methods — techniques the papers use, named apart from their topics
separate compilation · 1.1linkage · 1.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software developmentabstractFPGA-based accelerators are demonstrating significant absolute performance and energy efficiency compared with general-purpose CPUs. While FPGA computations can now be described in standard, programming languages, like C, development for FPGAs accelerators remains tedious and inaccessible to modern software engineers. Slow compiles (potentially taking tens of hours) inhibit the rapid, incremental refinement of designs that is the hallmark of modern software engineering. To address this issue, we introduce separate compilation and linkage into the FPGA design flow, providing faster design turns more familiar to software development. To realize this flow, we provide abstractions, compiler options, and compiler flow that allow the same C source code to be compiled to processor cores in seconds and to FPGA regions in minutes, providing the missing -O0 and -O1 options familiar in software development. This raises the FPGA programming level and standardizes the programming experience, bringing FPGA-based accelerators into a more familiar software platform ecosystem for software engineers. Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon |
ASPLOS | 7 |