The layout area and power consumption of a charge-scaling digital-to-analog converter (DAC) is typically dominated by the capacitor array. For a binary-weighted DAC, since the number of unit capacitors in the array increases exponentially with the number of bits, minimizing the size of the unit capacitor is crucial for controlling the layout area. A split DAC uses many fewer unit capacitors than the binary-weighted DAC, but requires the use of noninteger multiples of a unit capacitance; the choice of unit capacitor remains an important consideration. Smaller capacitors can be susceptible to larger amounts of noise and process mismatch, and can also be affected by mismatch in the parasitics of routing wires that connect the capacitors in the array: the latter is particularly significant in FinFET nodes. Together, these factors can degrade critical DAC performance metrics unless the unit capacitor is sufficiently large. This work proposes a systematic approach for selecting the unit capacitance value in both binary-weighted and split capacitor arrays for charge-scaling DACs. The proposed method selects a value that optimizes the nonlinearity metrics of a DAC, accounting for multiple factors that contribute to mismatch, flicker noise, and thermal noise. Our results demonstrate that by using a systematic methodology to size the unit capacitor, it is possible to overcome shifts due to process variation and noise for 6-bit to 14-bit DACs. Particularly for higher-resolution DACs, it is seen that the minimum unit capacitor value for binary-weighted DACs is lower than for split DACs, but the former incurs much larger area costs since it contains a significantly larger number of unit capacitors.

In FinFET nodes, high transistor power densities in a power amplifier (PA) lead to device self-heating (SH), degrading performance. This study investigates the impact of SH in large PA FinFET arrays. An encoder-decoder network, together with a long short-term memory model, is used for rapid and accurate thermal analysis. This fast analyzer helps better explore design optimizations than conventional computationally-expensive thermal solvers. The work explores methods for mitigating thermal effects in PAs by inserting dummy transistors within the array of active FinFET devices, and shows the impact of duty cycle and frequency on PA performance.

The layout area and power consumption of a binary-weighted capacitive digital-to-analog converter (DAC) increases exponentially with the number of bits. To meet linearity targets, unit capacitors should be large enough to limit errors caused by various sources of noise and those due to mismatch. This work proposes a systematic approach for minimizing the unit capacitance value that optimizes the linearity metrics of a DAC, accounting for multiple factors that contribute to mismatch, as well as the impact of flicker and thermal noise.

Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This article develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3-dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3-dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

This paper presents an overview of common-centroid (CC) layout styles, used in analog designs to overcome the impact of systematic variations. CC layouts must be carefully engineered to minimize the impact of mismatch. Algorithms for CC layout must be aware of routing parasitics, layout-dependent effects (for active devices), and the performance impact of layout choices. The optimal CC layout further depends on factors such as the choice of the unit device and the relative impact of uncorrelated and systematic variations. The paper also examines scenarios where non-CC layouts may be preferable to CC layouts.

The accuracy and linearity of capacitive digital-to-analog converters (DACs) depend on precise capacitor ratios, but these ratios are perturbed by process variations and parasitics. This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted capacitors in charge-sharing DACs. Parasitics also degrade the switching speed of a capacitor array, particularly in FinFET nodes with severe wire/via resistances. To overcome this, the capacitor array is placed and routed to optimize switching speed, measured by the 3dB frequency. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.