EDBT 2026 Demo / reviewers in the wild / expert
Vignesh Sundaresha
dblp:315/5188
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2023
0000-0003-3916-876XORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 1 · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 50% Energy-efficient computing · 44% Embedded and real-time systems · 6% | |
| Artificial intelligence
1 paper |
Vision and language · 50% Robot navigation and mapping · 50% | |
| Computer graphics and multimedia
1 paper |
Audio and music processing · 100% |
Topics — the 10 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › logic synthesis
circuit optimization |
0.7 | 1 | 2023 | Geometric Programming Approach to Glitch Minimization via Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Electronic design automation › physical design
gate sizing |
0.7 | 1 | 2023 | Geometric Programming Approach to Glitch Minimization via Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Energy-efficient computing › dynamic power reduction
glitch reduction |
0.7 | 1 | 2023 | Geometric Programming Approach to Glitch Minimization via Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Energy-efficient computing
low-power design |
0.7 | 1 | 2023 | Geometric Programming Approach to Glitch Minimization via Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Computer vision › Vision and language
audio-visual learning |
0.5 | 1 | 2021 | Localize to Binauralize: Audio Spatialization from Visual Sound Source Localization · ICCV 2021 |
Robotics › Robot navigation and mapping
sound source localization |
0.5 | 1 | 2021 | Localize to Binauralize: Audio Spatialization from Visual Sound Source Localization · ICCV 2021 |
Audio and music processing › spatial audio › binaural reproduction
binaural audio generation |
0.5 | 1 | 2021 | Localize to Binauralize: Audio Spatialization from Visual Sound Source Localization · ICCV 2021 |
Audio and music processing
spatial audio |
0.5 | 1 | 2021 | Localize to Binauralize: Audio Spatialization from Visual Sound Source Localization · ICCV 2021 |
Electronic design automation
timing analysis |
0.2 | 1 | 2023 | Geometric Programming Approach to Glitch Minimization via Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Embedded and real-time systems
timing constraints |
0.2 | 1 | 2023 | Geometric Programming Approach to Glitch Minimization via Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Methods — techniques the papers use, named apart from their topics
weakly supervised learning · 1.0multimodal learning · 1.0knowledge distillation · 1.0posynomial formulation · 0.7geometric programming · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Geometric Programming Approach to Glitch Minimization via Gate SizingabstractThe problem of gate sizing to meet timing specification while minimizing functional power/area is well understood and is solved by the use of geometric programs (GPs). While these area minimization GP (AM-GP) formulations minimize functional power, they do not address the problem of glitches. Glitches are extraneous transitions caused by signal arrival time imbalance at the input nodes of logic gates. A gate sizing algorithm, area-glitch minimization GP (AGM-GP), is proposed to reduce glitches while constraining area and adhering to a timing specification. Glitch reduction is achieved through signal arrival time balancing posed as posynomials in a GP formulation. Prior art does not exploit the complete power of gate sizing when reducing glitches in an attempt to meet the timing specification. In particular, the proposed formulation allows both upsizing and downsizing without causing any timing violation, at the expense of a marginal increase in area. Traditional downsizing methods can be used to further reduce glitches over and above the AGM-GP solution. Simulation results on the ISCAS-85 benchmark circuits show an overall reduction of 20.4% glitch power and 9.5% total power which is, respectively, 13.8% and 3.9% better than just downsizing the AM-GP solution. This power reduction was achieved with an average area increase of 4.2%. Karthikeyan Muthamizh Vithagan, Vignesh Sundaresha, Janakiraman Viraraghavan |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2021 | Localize to Binauralize: Audio Spatialization from Visual Sound Source LocalizationabstractVideos with binaural audios provide immersive viewing experience by enabling 3D sound sensation. Recent works attempt to generate binaural audio in a multimodal learning framework using large quantities of videos with accompanying binaural audio. In contrast, we attempt a more challenging problem – synthesizing binaural audios for a video with monaural audio in a weakly semi-supervised setting. Our key idea is that any down-stream task that can be solved only using binaural audios can be used to provide proxy supervision for binaural audio generation, thereby reducing the reliance on explicit supervision. In this work, as a proxy-task for weak supervision, we use Sound Source Localization with only audio. We design a two-stage architecture called Localize-to-Binauralize Network (L2BNet). The first stage of L2BNet is a Stereo Generation (SG) network employed to generate two-stream audio from monaural audio using visual frame information as guidance. In the second stage, an Audio Localization (AL) network is designed to use the synthesized two-stream audio to localize sound sources in visual frames. The entire network is trained end-to-end so that the AL network provides necessary supervision for the SG network. We experimentally show that our weakly-supervised framework generates two-stream audio containing binaural cues. Through user study, we further validate that our proposed approach generates binaural-quality audio using as little as 10% of explicit binaural supervision data for the SG network. Kranthi Kumar Rachavarapu, Aakanksha, Vignesh Sundaresha, A. N. Rajagopalan 0001 |
ICCV | 3 |