Resistive random-access memory (ReRAM)-based in-memory computing (IMC) systems offer significant advantages for efficient neural network inference. However, these systems are vulnerable to stuck-at faults (SAFs), which degrade inference accuracy-a challenge that becomes more pronounced in multilevel cell (MLC) configurations. A conventional fault mitigation technique, array-wise weight remapping (AWR), addresses SAFs but incurs significant hardware overhead. To overcome these limitations, we propose pseudo-array-wise weight remapping (PAWR), a novel method that integrates mux-wise weight remapping (MWR) and mux group remapping (MGR) to achieve costefficient fault tolerance. Experimental results demonstrate that even at a high 20% SAF rate, PAWR achieves accuracies within 0.7% of AWR, while significantly reducing area overhead by 86.5% and energy overhead by 72.4% compared to AWR.

Resistive random-access memory (ReRAM)-based in-memory computing (IMC) systems provide high energy efficiency and storage density for deep neural network (DNN) acceleration, but stuck-at faults (SAFs) substantially degrade reliability. Weight remapping (WR) can mitigate SAFs; however, existing approaches either ignore dataflow consistency or require additional hardware to restore it. We propose FREEMAP, an overhead-free WR algorithm that preserves dataflow consistency without runtime operations or hardware modifications. FREEMAP combines layer-wise filter reordering (LFR), which globally reorders filters across a layer for fault resilience, with row group remapping (RGR), which realigns the next layer's weight rows to the reordered outputs. Across diverse models and datasets, FREEMAP eliminates the hardware overhead of conventional WR, reducing area and energy to 0.02×-0.06× and 0.04×-0.14×, respectively. Compared with state-of-the-art dataflow-aware WR, it further reduces area and energy to 0.45×-0.47× and 0.52×-0.63× while maintaining comparable accuracy.

This paper addresses two critical challenges in analog In-Memory Computing (IMC) systems that limit their scalability and deployability: the computational unreliability caused by stuck-at faults (SAFs) and the high compilation overhead of existing fault-mitigation algorithms, namely Fault-Free (FF). To overcome these limitations, we first propose a novel multi-bit weight representation technique, termed row-column hybrid grouping, which generalizes conventional column grouping by introducing redundancy across both rows and columns. This structural redundancy enhances fault tolerance and can be effectively combined with existing fault-mitigation solutions. Second, we design a compiler pipeline that reformulates the fault-aware weight decomposition problem as an Integer Linear Programming (ILP) task, enabling fast and scalable compilation through off-the-shelf solvers. Further acceleration is achieved through theoretical insights that identify fault patterns amenable to trivial solutions, significantly reducing computation. Experimental results on convolutional networks and small language models demonstrate the effectiveness of our approach, achieving up to 8%p improvement in accuracy, 150 × faster compilation, and 2 × energy efficiency gain compared to existing baselines.

The advancement of neuromorphic devices (NDs) for processing deep neural networks has narrowed the accuracy gap with software-trained models. To accurately assess ND performance, reliable simulation frameworks for on-chip training are crucial. However, existing frameworks encounter difficulties accurately reflecting the characteristics of NDs in training simulations. Consequently, we introduce TraiNDSim, a novel framework that comprehensively evaluates the performance of NDs to address these difficulties. Specifically, we propose an advanced conductance normalization strategy called layer-wise normalization, which limits the weight range by taking the initial weight distribution into account. Additionally, our framework integrates three conductance models, notably refining one of the conventional models to depend solely on nonlinearity. Moreover, it features a bi-directional weight representation method with a unique conductance compensation technique. Our comprehensive analysis using TraiNDSim demonstrates its effectiveness in accurately reflecting the impact of ND parameters on training, promising more precise device performance evaluations. Our framework is available at https://github.com/donghyeokheo/TraiNDSim.

The ReRAM-based neuromorphic computing system (NCS) has been widely used as an energy-efficient platform for deep neural network (DNN) acceleration. However, ReRAM commonly suffers from stuck-at-fault (SAF), resulting in permanent device failure. SAF tolerance is an essential task to ensure the reliability of the system by minimizing the DNN inference accuracy degradation. Since hardware-based solutions incur additional overhead and power consumption, it is necessary to seek a solution that can be executed offline to mitigate the impact of SAF. In this work, we propose a decomposition-aware column re-mapping (DCR) for SAF tolerance in analog ReRAM arrays (RAs). Our DCR consists of the column re-mapping technique combined with fault-aware weight decomposition and an advanced sensitivity metric. As a result, it generates a final weight map optimized for the fault map. Our DCR achieves only about 1% loss of inference accuracy on CIFAR-10 and CIFAR-100 for the analog RAs with the SAF rate of 2% and 1%, respectively, without any hardware-based solution or re-training.

Convolutional weight mapping plays a stapling role in facilitating convolution operations on Processing-in-memory (PIM) architecture which is, at its essence, a matrix-vector multiplication (MVM) accelerator. Despite its importance, convolutional mapping methods are under-studied and existing mapping methods fail to exploit the sparse and redundant characteristics of heavily quantized convolutional weights, leading to low array utilization and ineffectual computations. To address these issues, this paper proposes a novel weight-aware activation mapping method where activations are mapped onto the memory cells instead of the weights. The proposed method significantly reduces the number of computing cycles by skipping zero-valued weights and merging those PIM array rows with the same weight values. Experimental results on ResNet-18 demonstrate that the proposed weight-aware activation mapping can achieve up to 90% energy saving and latency reduction compared to the conventional approaches.

We consider class incremental learning (CIL) problem, in which a learning agent continuously learns new classes from incrementally arriving training data batches and aims to predict well on all the classes learned so far. The main challenge of the problem is the catastrophic forgetting, and for the exemplar-memory based CIL methods, it is generally known that the forgetting is commonly caused by the classification score bias that is injected due to the data imbalance between the new classes and the old classes (in the exemplar-memory). While several methods have been proposed to correct such score bias by some additional post-processing, e.g., score re-scaling or balanced fine-tuning, no systematic analysis on the root cause of such bias has been done. To that end, we analyze that computing the softmax probabilities by combining the output scores for all old and new classes could be the main cause of the bias. Then, we propose a new method, dubbed as Separated Softmax for Incremental Learning (SS-IL), that consists of separated softmax (SS) output layer combined with task-wise knowledge distillation (TKD) to resolve such bias. Throughout our extensive experimental results on several large-scale CIL benchmark datasets, we show our SS-IL achieves strong state-of-the-art accuracy through attaining much more balanced prediction scores across old and new classes, without any additional post-processing.