Soheil Khadirsharbiyani

dblp:316/0380 · DBLP profile ↗
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4ranked-venue papers
2as first author
4since 2021 · last 2024
0000-0003-2473-6752ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021
YearPublicationVenuePosition
2024 SmartGraph: A Framework for Graph Processing in Computational Storage
abstract
Graph processing plays a pivotal role in numerous large-scale applications, including social and transportation networks. One of the primary challenges in handling large-scale graph data is its tendency to surpass DRAM capacities. Conventional methods focus on minimizing I/O latency by decreasing disk I/O requests via predictive value calculations. However, these techniques often struggle with inefficient partitioning strategies that elevate DRAM needs, underutilized predictive calculations, and incur considerable synchronization overheads.
Soheil Khadirsharbiyani, Nima Elyasi, Armin Haj Aboutalebi, Chun-Yi Liu 0002, Changho Choi, Mahmut T. Kandemir
SoCC1
2024 Minimizing Coherence Errors via Dynamic Decoupling
abstract
Quantum computing in the Noisy Intermediate-Scale Quantum (NISQ) era faces significant challenges due to the limitations in quantum gate fidelity and elevated error rates, which impede the successful execution of large-scale quantum circuits. One major source of errors in quantum computing is ’coherence errors’, which arise from the idle time during circuit execution. Specifically, factors such as uneven gate operations, hardware limitations, and qubit connectivity constraints collectively contribute to the formation of ’holes’ in quantum circuits, leading to ’idle qubits’. These idle periods, in turn, increase noise and error rates, thus negatively impacting the overall reliability of quantum circuits’ outputs.
Soheil Khadirsharbiyani, Movahhed Sadeghi, Mostafa Eghbali Zarch, Mahmut T. Kandemir
ICS1
2023 MBFGraph: An SSD-based External Graph System for Evolving Graphs
abstract
The challenge of executing extensive graph analyses in-memory intensifies with growing graph sizes. This has given rise to disk-based external graph analytics systems that prioritize cost-effective HDDs/SSDs over pricier memory solutions. In response to this issue, our paper introduces and assesses the MBFGraph external graph system. This system leverages millions of Bloom filters within 1KB or 2KB graph data blocks to diminish graph analysis execution delays. Through our innovative MBF-query and MBF-construct algorithms, MBFGraph utilizes these Bloom filters as approximate indices, enabling the reading of only pertinent sections of dynamic graph data, thereby facilitating scalable analytics. Our tests revealed that, on a 475GB graph, MBFGraph cut down the execution durations of BFS and Pagerank by 24% and 60% respectively, using a mere 4GB memory. This is in comparison to a sequential, tailored-for-workload, disk-based external graph analytics system.
Chun-Yi Liu 0002, Wonil Choi, Soheil Khadirsharbiyani, Mahmut T. Kandemir
SC3
2022 Athena: An Early-Fetch Architecture to Reduce on-Chip Page Walk Latencies
abstract
Large-scale applications from various domains are becoming increasingly irregular, posing significant strains on virtual memory performance. On the other hand, increasing hardware SRAM structures like TLB is becoming challenging due to technology scaling constraints imposed by the limitations of Moore's law. This emerging trend in applications, coupled with the lack of technology scaling in hardware, requires innovations at the hardware level to avoid expensive memory accesses for traversing page tables to keep page walk latencies in check.
Seyed Armin Vakil-Ghahani, Soheil Khadirsharbiyani, Jagadish Kotra, Mahmut T. Kandemir
PACT2