This brief presents an area-efficient noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) employing a parallel-delayed sampling (PDS) technique. PDS samples the residual voltages from multiple ADC conversion cycles to increase the NS effect, without the need for large integration capacitors of the typical cascaded passive integrators. A preamplifier is placed between the sampling capacitors and the integrator to avoid signal attenuation, while further reducing the area of the integrator. PDS and preamplifier introduce two left-half-plane poles to the noise transfer function (NTF) to boost the NS effect, while reducing the impact of the parasitic capacitance to essentially enhance the robustness. A prototype 9-bit NS-SAR ADC is designed in a 130-nm CMOS process. At an oversampling ratio (OSR) of 16, the proposed PDS NS-SAR ADC achieves 80.93-dB peak signal to noise and distortion ratio (SNDR) and provides 4.2 NS/area efficiency factor. It consumes a power of$23.46~\mu $W over a bandwidth of 19.53 kHz, achieving a Schreier figure of merit (FoM${}_{\mathrm {S}}$) of 170.13 dB.

This brief presents a CMOS inverter (INV)-based amplifier with local and system dual common-mode feedback (CMFB) loops through paralleled pseudo transconductors (PTs) for multichannel neural signal recording. The PT-INV forms a DC-coupled input to ensure a high input impedance, and local and system dual CMFB loops are introduced through the paralleled PT terminals of the INV. The local CMFB (L-CMFB) with the capacitor-reused topology not only reduces the die area and increases the differential-mode (DM) gain but also reduces the common-mode (CM) gain. The system CMFB (S-CMFB) loop detects the multiple CM outputs, and further increases the overall CMRR. The proposed PT-INV based instrumentation amplifiers (IAs) with dual CMFB loops are fabricated in a 0.18-$\mu $m CMOS process, and an overall CMRR of 87dB is achieved with a compact single-channel core area of 0.02mm2.

This article presents a Gm-controlled inverter (GC-INV) based amplifier with multiple common-mode feedback (CMFB) loops for multi-channel bio-signal recording. The GC-INV forms a DC-coupled input to ensure a high input impedance. The multi-CMFB, including twin local (TL), regional system (RS), and averaged system (AS) CMFB loops, is introduced through the paralleled GC terminals to provide multiple feedback paths. The TL-CMFB with capacitor-reused topology not only reduces the die area and increases the differential-mode gain, but also reduces the common-mode (CM) gain. The RS-CMFB mitigates the common-mode interference (CMI) due to the mismatch of the CM feedback paths. The AS-CMFB further mitigates the accumulated CMI from CM sampling paths. These CMFB loops avoid the design trade-off between the intrinsic CMRR and the efficiency of area and power. The proposed GC-INV based amplifier with multi-CMFB is fabricated in a 0.18-$\mu $m CMOS technology. It achieves an intrinsic CMRR of 97 dB, TCMRR of 78 dB, and the single-channel INV consumes a chip area of 0.008 mm2.

In this paper, a voltage-controlled oscillator (VCO) and phase detector (PD) based stimulation artifact (SA) removal scheme is proposed for simultaneous neural stimulation and recording. VCO is used to avoid the saturation of conventional front-end amplifier. The VCO converted signals are separated in the frequency and time domain. A PD in closed- loop recovers the neural signal from the converted signal, and a predicted SA amplitude helps removing the SA. Compared to other SA removal schemes, the proposed VCO-PD-based SA removal technique avoids the subtraction path at the input stage to ensure a high input impedance and achieves high linearity for continuous SA removal.

This brief proposes a parallel multiresidual (PMR) integrator to enhance the noise-shaping (NS) effect for successive approximation register (SAR) analog-to-digital converter (ADC). The PMR employs passive integrators in parallel to simultaneously integrate the average result of the multiple sequential residual voltages. The proposed PMR technique provides an alternative scheme to enhance the NS rather than increasing the order of the integrator to suppress the instability and power. A prototype 7-bit second-order NS-SAR ADC is designed and simulated in a 130-nm CMOS process. PMR increases the effective number of bits (ENOBs) to 10.6 bit, which enhances the NS effect of 3.6 bit. It achieves a peak signal-to-noise and distortion ratio (SNDR) of 65.84 dB over a bandwidth of 1.3 kHz at the oversampling ratio (OSR) of 16.