This article presents a four-channel interface application-specific integrated circuit (ASIC) for infrared focal plane arrays (IRFPAs), where each channel integrates a programmable gain amplifier (PGA) with wide-range input common-mode adjustment capability and a 16-bit hybrid analog-to-digital converter (ADC) with resistor-sharing technique (RST). The flash stage of the ADC performs 5-bit most significant bits (MSBs) conversion, whose results are transferred to thermometer-coded capacitor array in the successive approximation register (SAR) stage, ensuring high linearity while maintaining conversion speed. This hybrid architecture of the ADC uses the RST by sharing the resistor ladder between the flash and SAR stages, reducing power consumption. The interface ASIC fabricated in the 180-nm CMOS technology achieves an input common-mode adjustment range of 0.169–3.269V. Operating at 2 MS/s with a 3.3-V supply, it achieves an 88.1-dB signal-to-noise-and-distortion ratio (SNDR) and consumes 13.97 mW/channel. The Schreier figure-of-merit (FoM) of the ADC reaches 171.2 dB/channel. Measured differential and integral nonlinearity (DNL/INL) are −0.38/+0.49 least significant bits (LSBs) and −2.2/+1.4 LSB, respectively.

This article presents a novel data acquisition system (DAS) designed for area-sensitive applications, including automotive instrumentation, launch vehicles, and satellites, which require efficient area utilization and full-swing input/output capabilities for diverse sensors. Traditional approaches to achieving full swing, such as using CMOS input transistors or generating negative voltage via charge pumps, either result in high harmonic distortion (HD) or complicate chip design. To address these challenges, we propose a complementary analog front-end (CAFE) that shifts the input signal by a fixed voltage, enabling operation in a more linear region while employing feedback to minimize HD. The system incorporates two analog-to-digital converters (ADCs) that convert the input signal and subtract the digital output of the common mode voltage ($V_{\text {CM}}$), facilitating effective data fusion for complete AD conversion. Fabricated using a 180-nm 1P5M BCD process, the DAS consumes 118.81 mW from a 5.0-V power supply, providing 64 channels in a compact area of$4.0\times 3.2$mm. At a sampling rate of 1 MS/s, it achieves an effective number of bits (ENoBs) of 13.16, with a power consumption of 1.856 mW per channel and a dynamic range of 83.3 dB, resulting in an impressive figure of merit per channel (FoMS/Ch) of 165.3 dB.

This paper presents an event-driven readout integrated circuit (ROIC) for imaging and target-tracking infrared focal plane arrays (IRFPAs). The pixel circuit consists of event detection (ED) and imaging and trace detection (ITD). Based on the dynamic vision sensor (DVS) structure, ED encodes the temporal changes of infrared radiation into synchronized 1.5-bit events and transmits them to the off-chip postprocessor. When a moving target is recognized, the region of interest (ROI) window address will be feedback to ROIC and read out the image and trace information provided by ITD, which is based on infinite impulse response in the analog domain. These absolute intensities and multi-frame fused trace allow the post-processor to complete high-accuracy agile action recognition. This ROIC provides a spatiotemporal redundant compression and energy-efficient solution for fast-moving object detection and analysis. A prototype based on a 16×16 array of 20 µm pixel-pitch has been fabricated using a 0.18 µm 1P5M CMOS process, consuming [email protected] event and image frame frequency. Detailed test and measurement results of the prototype are presented.

This paper presents a low-power and energy-efficient capacitance-to-digital converter (CDC) for a single-end sensor based on correlated double sampling (CDS) technology. The CDS is accomplished by two opposite conversions, which reuse the comparator, CSENS, and CDAC. The proposed CDC eliminates the parasitic-dependent error caused by the comparator’s offset without extra consumption through the CDS. The simulation results show that the CDC can eliminate low-frequency interference and achieve anti-common-mode interference capabilities similar to differential circuits. To achieve low noise and high energy efficiency, the CDC employs a floating inverter amplifier (FIA) as the pre-amplifier of the comparator. Implemented in a 0.18 μm CMOS process, it consumes 0.91 μW from a 1.2 V supply. The simulation results show an effective number of 11.69 bits and an energy efficiency of 27.5 fJ per conversion step.

A compact low-noise digital pixel with 15-bit pixel-level two-step analog-to-digital converter (ADC) is presented in this paper. The coarse quantization adopts a 10-bit pulse frequency modulation conversion with a proposed threephase charge-reset circuit. The charge-reset circuit reduces the reset noise charge which is the major noise of this pixel. The fine quantization is implemented by a 5-bit single-slope ADC. It reuses most of the coarse quantization circuit to realize high precision quantization in compact pixel. A 640×512 readout integrated circuit for infrared focal plane array with the 15μm pitch digital pixel is designed in the 0.18 μm1P5M CMOS process for verification. Post-layout simulation results of the digital pixel show that the RMS noise at maximum signal is 0.51LSB, and the integral nonlinearity is +2.3LSB/-3.0LSB. The power consumption per pixel is only 57. 2nW at 120fps.