Camouflage Images Generation (CIG) is an emerging research area that focuses on synthesizing images in which objects are harmoniously blended and exhibit high visual consistency with their surroundings. Existing methods perform CIG by either fusing objects into specific backgrounds or outpainting the surroundings via foreground object-guided diffusion. However, they often fail to obtain natural results because they overlook the logical relationship between camouflaged objects and background environments. To address this issue, we propose CT-CIG, a Controllable Text-guided Camouflage Images Generation method that produces realistic and logically plausible camouflage images. Leveraging Large Visual Language Models (VLM), we design a Camouflage-Revealing Dialogue Mechanism (CRDM) to annotate existing camouflage datasets with high-quality text prompts. Subsequently, the constructed image-prompt pairs are utilized to finetune Stable Diffusion, incorporating a lightweight controller to guide the location and shape of camouflaged objects for enhanced camouflage scene fitness. Moreover, we design a Frequency Interaction Refinement Module (FIRM) to capture high-frequency texture features, facilitating the learning of complex camouflage patterns. Extensive experiments, including CLIPScore evaluation and camouflage effectiveness assessment, demonstrate the semantic alignment of our generated text prompts and CT-CIG's ability to produce photorealistic camouflage images.

Synthesizing circuits to achieve better PPA is crucial, particularly in datapath netlists with various arithmetic operators. The verification relies on the Combinational Equivalence Checking (CEC) techniques, checking the equivalence of two combinational circuits. Contemporary CEC tools commonly utilize SAT as the principal reasoning engine, employing a SAT-sweeping algorithm, which sequentially confirms the equivalence of internal pairs in topological order, merging verified equivalents to reduce the netlist’s scale. Nonetheless, datapath circuits frequently comprise pairs of nodes characterized by relatively limited transitive fan-in cones, yet these nodes display a pronounced density of XOR chains. This particular arrangement presents considerable obstacles for SAT solvers. To address this, exact probability-based simulation (EPS) provides an effective solution, but its high memory requirements limit its applicability. This article proposes a hybrid CEC prover, hybridCEC , and its parallel version, paraHCEC . Firstly, we decrease the memory requirements of the EPS method and integrate it into the SAT-sweeping framework. Secondly, we propose a dynamic engine selection heuristic for SAT and EPS, based on XOR chain density. Thirdly, we improve efficiency by identifying and reducing redundant engine calls by detecting regularity in the circuits. Finally, we parallelize the internal SAT and EPS engines, resulting in a highly efficient parallel CEC prover. Extensive experiments on industrial datapath circuit benchmarks demonstrate that our method significantly outperforms the state-of-the-art prover ABC “&cec”, achieving up to 100× speedups on 40% of instances and over 1000× speedups on 14%. Moreover, our 64-thread parallel version achieved an impressive 70× speedup, highlighting its scalability and effectiveness.

In modern digital circuit design, verifying the equivalence of arithmetic circuits is a significant and challenging task. This paper introduces a new circuit solver based on the Conflict-Driven Clause Learning (CDCL) algorithm, which integrates structural elimination techniques to reduce the number of variables and clauses while maintaining the circuit structure. Additionally, branching heuristics have been enhanced specifically for the structure of arithmetic circuits. Experimental results demonstrate that X-SAT significantly outperforms best previous circuit solver could be found on all benchmarks. Further, X-SAT performs better than the state-of-the-art CNF-based SAT solvers on complex arithmetic circuits, underscoring its significant potential in the field of circuit design verification.

Camouflaged Object Detection (COD) presents a formidable challenge in computer vision due to the inherent difficulty of distinguishing the foreground from the background when objects are camouflaged. Inspired by research on optical imaging that proves the significance of depth of field for enhancing visual clarity and object separation, we introduce depth images into the COD framework to augment RGB data. In this paper, we propose a novel FocusNet that mimics the focusing process in photography. Specifically, we first propose a Dual-Modality Fusion (DMF) module to collaboratively learn deep features from both RGB and depth modalities, framing the whole concealed scene. Then, we propose another Depth Feature Focusing (DFF) module to fully exploit the localization cues in depth images, focusing on the foreground region. Finally, we propose the Hierarchical Feature Decoder (HFD) to generate accurate masks from multi-level features, capturing the camouflaged target. Extensive experiments demonstrate the effectiveness of the proposed FocusNet.

Camouflage images generation refers to concealing a salient object within a specific background by integrating its appearance with the surrounding environment. Previous approaches typically perform it by blending foreground and background images, which often suffer from 1) insufficient or excessive concealment, and 2) lack of effective evaluation metrics for assessing camouflage quality. To address these issues, we propose an Adaptive Camouflage Synthesizing network, named ACS-Net, which aims to generate images that effectively camouflage the object and minimize its salience. Specifically, a Multi-level Feature Aggregation Module (MFFM) is designed to improve the granularity of feature extraction, along with a Dual-branch Attention Enhancement Module (DAEM) for fore-back weight importance measurement to avoid excessive concealment. Subsequently, a Position-aligned Feature Fusion Module (PFFM) is utilized to effectively camouflage objects to an optimal extent guided by structural similarity. Furthermore, we employ detection methods for both camouflaged and salient objects to process our generated images as an unbiased evaluation for camouflage quality. Comprehensive experiments demonstrate that ACS-Net outperforms existing methods and is capable of generating high-quality camouflage images with an appropriate balance of concealment and salience. Code is available at https://github.com/NikoNairre/ACS-Net.

Given the wide adoption of multimodal sensors (e.g., camera, lidar, radar) byautonomous vehicles (AVs), deep analytics to fuse their outputs for a robust perception become imperative. However, existing fusion methods often make two assumptions rarely holding in practice: i) similar data distributions for all inputs and ii) constant availability for all sensors. Because, for example, lidars have various resolutions and failures of radars may occur, such variability often results in significant performance degradation in fusion. To this end, we present t-READi, an adaptive inference system that accommodates the variability of multimodal sensory data and thus enables robust and efficient perception. t-READi identifies variation-sensitive yetstructure-specificmodel parameters; it then adapts only these parameters while keeping the rest intact. t-READi also leverages a cross-modality contrastive learning method to compensate for the loss from missing modalities. Both functions are implemented to maintain compatibility with existing multimodal deep fusion methods. The extensive experiments evidently demonstrate that compared with the status quo approaches, t-READi not only improves the average inference accuracy by more than 6% but also reduces the inference latency by almost 15× with the cost of only 5% extra memory overhead in the worst case under realistic data and modal variations.

Abstract Satisfiability Modulo Theories on arithmetic theories have significant applications in many important domains. Previous efforts have been mainly devoted to improving the techniques and heuristics in sequential SMT solvers. With the development of computing resources, a promising direction to boost performance is parallel and even distributed SMT solving. We explore this potential in a divide-and-conquer view and propose a novel dynamic parallel framework with variable-level partitioning. To the best of our knowledge, this is the first attempt to perform variable-level partitioning for arithmetic theories. Moreover, we enhance the interval constraint propagation algorithm, coordinate it with Boolean propagation, and integrate it into our variable-level partitioning strategy. Our partitioning algorithm effectively capitalizes on propagation information, enabling efficient formula simplification and search space pruning. We apply our method to three state-of-the-art SMT solvers, namely CVC5, OpenSMT2, and Z3, resulting in efficient parallel SMT solvers. Experiments are carried out on benchmarks of linear and non-linear arithmetic over both real and integer variables, and our variable-level partitioning method shows substantial improvements over previous partitioning strategies and is particularly good at non-linear theories.

In the application of IC design for microprocessors, there are often demands for optimizing the implementation of datapath circuits, on which various arithmetic operations are performed. Combinational equivalence checking (CEC) plays an essential role in ensuring the correctness of design optimization. The most prevalent CEC algorithms are based on SAT sweeping, which utilizes SAT to prove the equivalence of the internal node pairs in topological order, and the equivalent nodes are merged. Datapath circuits usually contain equivalent pairs for which the transitive fan-in cones are small but have a high XOR chain density, and proving such node pairs is very difficult for SAT solvers. An exact probability-based simulation (EPS) is suitable for verifying such pairs, while this method is not suitable for pairs with many primary inputs due to the memory cost. We first reduce the memory cost of EPS and integrate it to improve the SAT sweeping method. Considering the complementary abilities of SAT and EPS, we design an engine selection heuristic to dynamically choose SAT or EPS in the sweeping process, according to XOR chain density. Our method is further improved by reducing unnecessary engine calls by detecting regularity. Experiments on a benchmark suite from industrial datapath circuits show that our method is much faster than the state-of-the-art CEC tool namely ABC ‘&cec’ on nearly all instances, and is more than 100× faster on 30% of the instances, 1000× faster on 12% of the instances.