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Daniel P. Lulich

dblp:317/6552 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 50% Hardware accelerators and domain-specific architectures · 25% Processor architecture and microarchitecture · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
array processor
0.011996
Image processing using one-dimensional processor arrays · Proc. IEEE 1996
Hardware accelerators and domain-specific architectures
image processing accelerator
0.011996
Image processing using one-dimensional processor arrays · Proc. IEEE 1996
Parallel and multicore computing › parallel architecture
linear array processors
0.011996
Image processing using one-dimensional processor arrays · Proc. IEEE 1996
Processor architecture and microarchitecture
SIMD
0.011996
Image processing using one-dimensional processor arrays · Proc. IEEE 1996

Methods — techniques the papers use, named apart from their topics

amdahl's law · 0.0
YearPublicationVenuePosition
1996 Image processing using one-dimensional processor arrays
abstract
The first half of this paper presents the design rationale for CNAPS, a specialized one-dimensional (1-D) processor array developed by Adaptive Solutions Inc. In this context, we discuss the problem of Amdahl's law which severely constrains special-purpose architectures. We also discuss specific architectural decisions such as the kind of parallelism, the computational precision of the processors, on-chip versus off-chip processor memory, and-most importantly-the interprocessor communication architecture. We argue that, for our particular set of applications, a 1-D architecture gives the best "bang for the buck", even when compared to the more traditional two-dimensional (2-D) architecture. The second half of this paper describes how several simple algorithms map to the CNAPS array. Our results show that the CNAPS 1-D array offers excellent performance over a range of IP algorithms. We also briefly look at the performance of CNAPS as a pattern recognition engine because many image processing and pattern recognition problems are intimately related.
Dan W. Hammerstrom, Daniel P. Lulich
Proc. IEEE2