Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Benoit De Lescure

dblp:317/6689 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 75% Embedded and real-time systems · 25%
Computer graphics and multimedia
1 paper
Image and video processing · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel computing
heterogeneous parallelism
0.011996
The implementation of P3/I, a parallel architecture for video real-time processing: a case study · Proc. IEEE 1996
Parallel and multicore computing
parallel architecture
0.011996
The implementation of P3/I, a parallel architecture for video real-time processing: a case study · Proc. IEEE 1996
Parallel and multicore computing
parallel programming models
0.011996
The implementation of P3/I, a parallel architecture for video real-time processing: a case study · Proc. IEEE 1996
Embedded and real-time systems › real-time signal processing
real-time video processing
0.011996
The implementation of P3/I, a parallel architecture for video real-time processing: a case study · Proc. IEEE 1996
Image and video processing › real-time image processing
real-time video processing
0.011996
The implementation of P3/I, a parallel architecture for video real-time processing: a case study · Proc. IEEE 1996
YearPublicationVenuePosition
1996 The implementation of P3/I, a parallel architecture for video real-time processing: a case study
abstract
This paper provides a tutorial on the motivations, design, and applications of parallel processing applied to video real-time, illustrated by the experience gained in the implementation of the P/sup 3/I machine. Its main purpose is to highlight the motivations for such a development the basic implementation choices, the major difficulties encountered and how they have been solved. Through these studies we found that parallel processing is well-suited to video real-time, when programmable implementations are considered. There are many outcomes of the P/sup 3/I project, ranging from architectural considerations to parallel algorithms optimizations, and programming methodology. We want to emphasize three conclusions. First, programming an architecture composed of different parallel paradigms in a given architecture is tractable, and this heterogeneity is cost effective and efficient in terms of processing performances. Second, concerning the well known debate about how to match parallel architectures and image processing "levels" we conclude that the key is not to discuss Flynn's taxonomy (i.e., data versus tasks parallelism) but to consider how the parallelism grain evolves within a whole application. Third, we confirm that in the field of image processing, the efficiency of parallelism can only be gained if algorithms developers think "parallel"; this result seems to be obvious, but just consider the trends of recent RISC processors, embedding more and more parallelism, and claiming at a compatibility with existing sequential softwares.
Marie-Jean Colaitis, Jean-Luc Jumpertz, Benoit Guerin, Bruno Cheron, Fabien Battini, Benoit De Lescure, Eric Gautier, Jean-Pierre Geffroy
Proc. IEEE6