This paper presents a fully integrated reconfigurable single-channel IC with high energy efficiency for bio-signal acquisition in Internet-of-Medical Things (IoMT) systems. The overall signal chain consists of a capacitively-coupled instrumentation amplifier (CCIA) and a 16-bit delta-sigma ($\Delta$$\Sigma$) ADC. The ADC is directly driven by the CCIA without a traditional driver stage. The folded path of the first stage in CCIA is sliced for reconfigurable noise levels. In addition, a single-stage floating inverter amplifier (FIA) assisted by the correlated-level-shifting (CLS) technique is employed in the switched-capacitor (SC)$\Delta$$\Sigma$modulator for fully dynamic operation with sufficient DC gain. Fabricated in 180-nm CMOS, the CCIA achieves an input-referred noise level ranging from 35.8 to 67 nV/$\surd$Hz with a best noise-efficiency factor (NEF) of 5.54. It corresponds to an integrated noise ranging from 0.63 to 1.16$\mu$$\text{V}_\text{rms}$(0.5-100 Hz) and 1.93 to 3.51$\mu$$\text{V}_\text{rms}$(0.1-3 kHz), respectively. The ADC achieves a peak SNDR of 92.6 dB for a 2.3-$\text{V}_\text{pp}$differential input and can support 16$\times$power/BW reconfigurability with ENOB$>$15 bit. The complete system occupies an active area of 0.56 mm$^{2}$and achieves 85.7-dB system SNDR over a 500 Hz BW with an OSR of 128. It consumes 36.8$\mu$W from a 1.8-V supply, corresponding to an SNDR-based Schreier FoM of 157 dB. Biological measurement is demonstrated successfully, and the results verify that the proposed IC is applicable to high-quality ExG signal acquisition.

This article presents a fully dynamic switched-capacitor zoom ADC with 1st-order interstage leakage shaping (ILS). Noise shaping capability is integrated into the coarse stage by a low-cost error-feedback (EF) path, effectively mitigating quantization noise leakage in the traditional zoom architecture due to the non-unity STF. In addition, a swing-enhanced floating inverter amplifier (FIA) architecture is proposed for improved linearity as well as fully dynamic operations. The prototype ADC is fabricated in a 65-nm CMOS process and occupies an active area of 0.22 mm2. With a 1.2-V supply, it achieves 98.1-dB peak SNDR over a 20-kHz bandwidth with 142.8$\mu $W power consumption, resulting in a DR-based Schreier FoM of 182.9 dB and an SNDR-based FoM of 179.5 dB, respectively. According to the measurement results, 8$\times $power/BW configurability can be achieved by the zoom ADC while maintaining SNDR above 98 dB.

This paper presents a$G_{m}$-C integrator-implanted DC servo loop (GMCI2-DSL) and a bulk-driven ripple reduction loop (BD-RRL) for bio-potential readout analog-front-end (AFE) amplifier. The proposed bio-potential readout AFE amplifier employs the GMCI2-DSL and BD-RRL to achieve low noise and significant total harmonic distortion (THD) with small ripple amplitude. A prototype has been taped out using a 0.18-$\mu \text{m}$standard CMOS technology, and the core circuit occupies 880$\mu \text{m}\,\,\times $630$\mu \text{m}$. The mid-band gain is about 40 dB with a 1.3-V supply voltage, and the chip’s quiescent power is 10.8$\mu \text{W}$. The measured results show that the input-referred noise density is 26 nV/$\surd $Hz, and the input-referred integrated noise in the range from 0.5 Hz to 500 Hz is 0.93$\mu V_{rms}$. The measured THD of a 5-$\text{m}V_{pp}$input sinusoidal signal at 5.1 Hz is −64.3 dB without any input offset. The amplitude of residue ripple is achieved as 197.8$\mu \text{V}$around chopping frequency ($f_{ch}$) by ripple suppression. High-fidelity and real-time electrocardiogram (ECG) signals are acquired.

The fault diagnosability of a network indicates the self-diagnosis ability of the network, thus it is an important measure of robustness of the network. As a neoteric feature for measuring fault diagnosability, the r -component diagnosability ct r (G) of a network G imposes the restriction that the number of components is at least r in the remaining network of G by deleting faulty set X , which enhances the diagnosability of G . In this article, we establish the r -component diagnosability for n -dimensional hierarchical cubic network HCN n , and we show that, under both PMC model and MM* model, the r -component diagnosability of HCN n is rn -½( r -1) r +1 for n ≥ 2 and 1≤ r≤ n-1 . Moreover, we introduce the concepts of 0-PMC subgraph and 0-MM* subgraph of HCN n . Then, we make use of 0-PMC subgraph and 0-MM* subgraph of HCN n to design two algorithms under PMC model and MM* model, respectively, which are practical and efficient for component fault diagnosis of HCN n . Besides, we compare the r -component diagnosability of HCN n with the extra conditional diagnosability, diagnosability, good-neighbor diagnosability, pessimistic diagnosability, and conditional diagnosability, and we verify that the r -component diagnosability of HCN n is higher than the other types of diagnosability.