This work presents a self-healing runtime for AI accelerators on SRAM-based FPGAs that combines online fault detection with fine-grained partial reconfiguration to ensure continuous inference execution. The framework dynamically isolates and repairs faulty regions while remapping workloads to healthy resources, eliminating the need for redundant hardware and system downtime. The proposed approach reduces recovery latency by 3 orders of magnitude compared to the state-of-the-art.

Reliable anomaly detection in satellite telemetry is critical for mission success, yet traditional threshold-based methods struggle with complex and evolving patterns.This work presents machine learning (ML) techniques to analyze high-dimensional telemetry data.Evaluations of real-world satellite telemetry datasets demonstrate the potential of ML to enhance spacecraft health monitoring and reduce manual intervention.

The rapid increase in the complexity of Field-Programmable Gate Arrays (FPGAs) is significantly impacting the efficiency of the design implementation flow. In particular, the routing process presents challenges in achieving computational efficiency and reducing time-to-solution due to the increasing on-chip resources and device complexity. This work introduces a novel router that leverages optimized data structures and memory access patterns to minimize memory consumption. Experimental results prove how the proposed approach can significantly reduce time-to-solution, identifying memory consumption as a barrier to achieving scalability and proposing solutions based on FPGA modular architecture to face it, achieving an average memory usage reduction of about 90 % and an average decrease of routing time of 40 %.

Due to their high performance and flexibility, FPGAs have become an attractive solution for space applications. However, SRAM-based FPGAs are particularly sensitive to radiation-induced Single Event Effects that may lead to configuration memory corruption. We propose a methodology for enhancing the reliability of redundant design implemented on FPGAs. Statically analyzing the implementation of the circuit to identify and reduce the single points of failure of redundant systems, we can increase the system's robustness by controlling the placement phase.

In recent years, the growth of interest in adopting deep neural network techniques across various domains led to new architectures for supporting the required computational effort. Tensor Processing Units (TPUs), which are based on a systolic array matrix multiplication unit (MMU), became widely popular thanks to their specific structure suitable for Artificial Intelligence. This work investigates Single Event Transient (SET) effects on TPU’s MMU. The analysis demonstrates the impact of SETs on the functionality of MMU when executing digital image processing filtering. The experimental results identify the static and dynamic SET sensitivity of TPU and depict meaningful information on the data dependency of the filters’ kernel values.

In this study, we introduce a new runtime fault detection technique for systolic array accelerators oriented to neural network applications. The method exploits the functional path of the systolic array to compute and process checksum values during the execution of the current application instructions flow and integrates self-testing capabilities within the systolic array Instruction Set Architecture. The proposed technique does not require additional hardware self-testing modules, and the test pattern penalty is limited to 3 clock cycles independent of the size of the systolic array. Experimental analysis performed with fault injection campaigns demonstrates full fault detection capabilities of stuck-at faults with an average computing overhead 4 times lower than state-of-the-art solutions. Additionally, our approach exhibits diminished hardware overhead in contrast to conventional techniques.

Last decade, the RISC-V soft processor has become popular due to the benefits such as transparency and availability of hardware implementations on reconfigurable devices such as SRAM-based FPGAs. However, these devices are highly sensitive to high-energy particles. In this work, we propose an implementation methodology that ranges from the hardening method applied at the Register Transfer Level (RTL) to the optimization of layout techniques acting on the place & route of the design. As a case study, the TMR-hardened Arithmetic Logic Unit (ALU) of the RISC-V soft processor implementation was taken and its reliability under different design layouts has been analyzed using fault injection campaigns. Experimental results show that the design reliability can be improved by applying ad hoc layout customization..